Lines Matching refs:dbi_base
47 void *dbi_base; member
219 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & in rk_pcie_get_link_speed()
225 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & in rk_pcie_get_link_width()
233 void __iomem *base = rk_pcie->dbi_base; in rk_pcie_writel_ob_unroll()
241 void __iomem *base = rk_pcie->dbi_base; in rk_pcie_readl_ob_unroll()
250 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); in rk_pcie_dbi_write_enable()
256 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); in rk_pcie_dbi_write_enable()
275 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); in rk_pcie_setup_host()
276 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); in rk_pcie_setup_host()
279 clrsetbits_le32(rk_pcie->dbi_base + PCI_INTERRUPT_LINE, in rk_pcie_setup_host()
283 clrsetbits_le32(rk_pcie->dbi_base + PCI_PRIMARY_BUS, in rk_pcie_setup_host()
287 clrsetbits_le32(rk_pcie->dbi_base + PCI_PRIMARY_BUS, in rk_pcie_setup_host()
293 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); in rk_pcie_setup_host()
296 setbits_le32(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, in rk_pcie_setup_host()
316 clrsetbits_le32(pci->dbi_base + PCIE_LINK_CAPABILITY, in rk_pcie_configure()
319 clrsetbits_le32(pci->dbi_base + PCIE_LINK_CTL_2, in rk_pcie_configure()
422 va_address = (uintptr_t)pcie->dbi_base; in set_cfg_address()
736 priv->dbi_base = (void *)dev_read_addr_index(dev, 0); in rockchip_pcie_parse_dt()
737 if (!priv->dbi_base) in rockchip_pcie_parse_dt()
740 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); in rockchip_pcie_parse_dt()