Lines Matching refs:reg_set16
177 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
182 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up()
187 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); in comphy_pcie_power_up()
192 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
197 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); in comphy_pcie_power_up()
202 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up()
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
219 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
225 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, in comphy_pcie_power_up()
232 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
235 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_pcie_power_up()
240 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0), in comphy_pcie_power_up()
363 reg_set16(phy_addr(USB3, reg), data, mask); in usb3_reg_set16()
698 reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF); in comphy_sgmii_phy_init()
763 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), in comphy_sgmii_power_up()
770 reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel); in comphy_sgmii_power_up()
777 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), in comphy_sgmii_power_up()
781 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL), in comphy_sgmii_power_up()
798 reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask); in comphy_sgmii_power_up()
841 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); in comphy_sgmii_power_up()
844 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_sgmii_power_up()