Lines Matching refs:MSCC_P
88 MSCC_P(0, SG0, NONE, NONE);
89 MSCC_P(1, SG0, NONE, NONE);
90 MSCC_P(2, SG0, NONE, NONE);
91 MSCC_P(3, SG0, NONE, NONE);
92 MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI);
93 MSCC_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
94 MSCC_P(6, UART, TWI_SCL_M, NONE);
95 MSCC_P(7, UART, TWI_SCL_M, NONE);
96 MSCC_P(8, SI, TWI_SCL_M, IRQ0_OUT);
97 MSCC_P(9, SI, TWI_SCL_M, IRQ1_OUT);
98 MSCC_P(10, PTP2, TWI_SCL_M, SFP0);
99 MSCC_P(11, PTP3, TWI_SCL_M, SFP1);
100 MSCC_P(12, UART2, TWI_SCL_M, SFP2);
101 MSCC_P(13, UART2, TWI_SCL_M, SFP3);
102 MSCC_P(14, MIIM1, TWI_SCL_M, SFP4);
103 MSCC_P(15, MIIM1, TWI_SCL_M, SFP5);
104 MSCC_P(16, TWI, NONE, SI);
105 MSCC_P(17, TWI, TWI_SCL_M, SI);
106 MSCC_P(18, PTP0, TWI_SCL_M, NONE);
107 MSCC_P(19, PTP1, TWI_SCL_M, NONE);
108 MSCC_P(20, RECO_CLK0, TACHO, NONE);
109 MSCC_P(21, RECO_CLK1, PWM, NONE);