Lines Matching refs:MSCC_P
122 MSCC_P(0, SIO, NONE, NONE);
123 MSCC_P(1, SIO, NONE, NONE);
124 MSCC_P(2, SIO, NONE, NONE);
125 MSCC_P(3, SIO, NONE, NONE);
126 MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
127 MSCC_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
128 MSCC_P(6, UART, NONE, NONE);
129 MSCC_P(7, UART, NONE, NONE);
130 MSCC_P(8, SPI, SFP0, TWI_SCL_M);
131 MSCC_P(9, PCI_WAKE, SFP1, SPI);
132 MSCC_P(10, PTP0, SFP2, TWI_SCL_M);
133 MSCC_P(11, PTP1, SFP3, TWI_SCL_M);
134 MSCC_P(12, REF_CLK0, SFP4, TWI_SCL_M);
135 MSCC_P(13, REF_CLK1, SFP5, TWI_SCL_M);
136 MSCC_P(14, REF_CLK2, IRQ0_OUT, SPI);
137 MSCC_P(15, REF_CLK3, IRQ1_OUT, SPI);
138 MSCC_P(16, TACHO, SFP6, SPI);
139 MSCC_P(17, PWM, NONE, TWI_SCL_M);
140 MSCC_P(18, PTP2, SFP7, SPI);
141 MSCC_P(19, PTP3, SFP8, SPI);
142 MSCC_P(20, UART2, SFP9, SPI);
143 MSCC_P(21, UART2, NONE, NONE);
144 MSCC_P(22, MIIM1, SFP10, TWI2);
145 MSCC_P(23, MIIM1, SFP11, TWI2);
146 MSCC_P(24, TWI, NONE, NONE);
147 MSCC_P(25, TWI, SFP12, TWI_SCL_M);
148 MSCC_P(26, TWI_SCL_M, SFP13, SPI);
149 MSCC_P(27, TWI_SCL_M, SFP14, SPI);
150 MSCC_P(28, TWI_SCL_M, SFP15, SPI);
151 MSCC_P(29, TWI_SCL_M, NONE, NONE);
152 MSCC_P(30, TWI_SCL_M, NONE, NONE);
153 MSCC_P(31, TWI_SCL_M, NONE, NONE);
154 MSCC_P(32, TWI_SCL_M, NONE, NONE);
155 MSCC_P(33, RCVRD_CLK0, NONE, NONE);
156 MSCC_P(34, RCVRD_CLK1, NONE, NONE);
157 MSCC_P(35, RCVRD_CLK2, NONE, NONE);
158 MSCC_P(36, RCVRD_CLK3, NONE, NONE);