Lines Matching refs:mask
279 int mask = info->vsel_mask; in _buck_set_value() local
291 __func__, uvolt, buck + 1, info->vsel_reg, mask, val); in _buck_set_value()
294 pmic_clrsetbits(pmic, info->vsel_reg, mask, val); in _buck_set_value()
298 return pmic_clrsetbits(pmic, info->vsel_reg, mask, val); in _buck_set_value()
304 uint mask, value, en_reg; in _buck_set_enable() local
326 mask = 1 << buck; in _buck_set_enable()
333 ret = pmic_clrsetbits(pmic, REG_DCDC_EN, mask, in _buck_set_enable()
334 enable ? mask : 0); in _buck_set_enable()
364 int mask = info->vsel_mask; in _buck_set_suspend_value() local
376 __func__, uvolt, buck + 1, info->vsel_sleep_reg, mask, val); in _buck_set_suspend_value()
378 return pmic_clrsetbits(pmic, info->vsel_sleep_reg, mask, val); in _buck_set_suspend_value()
384 uint mask = 0; in _buck_get_enable() local
391 mask = 1 << (buck - 4); in _buck_get_enable()
394 mask = 1 << buck; in _buck_get_enable()
400 mask = 1 << buck; in _buck_get_enable()
408 mask = 1 << buck; in _buck_get_enable()
412 mask = 1 << 1; in _buck_get_enable()
421 return ret & mask ? true : false; in _buck_get_enable()
426 uint mask = 0; in _buck_set_suspend_enable() local
433 mask = 1 << buck; in _buck_set_suspend_enable()
434 ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask, in _buck_set_suspend_enable()
435 enable ? mask : 0); in _buck_set_suspend_enable()
439 mask = 1 << buck; in _buck_set_suspend_enable()
440 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF1, mask, in _buck_set_suspend_enable()
441 enable ? 0 : mask); in _buck_set_suspend_enable()
446 mask = 1 << buck; in _buck_set_suspend_enable()
448 mask = 1 << 5; /* BUCK5 for RK809 */ in _buck_set_suspend_enable()
449 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, in _buck_set_suspend_enable()
450 enable ? mask : 0); in _buck_set_suspend_enable()
463 uint mask = 0; in _buck_get_suspend_enable() local
468 mask = 1 << buck; in _buck_get_suspend_enable()
472 ret = val & mask ? 1 : 0; in _buck_get_suspend_enable()
476 mask = 1 << buck; in _buck_get_suspend_enable()
480 ret = val & mask ? 0 : 1; in _buck_get_suspend_enable()
485 mask = 1 << buck; in _buck_get_suspend_enable()
487 mask = 1 << 5; /* BUCK5 for RK809 */ in _buck_get_suspend_enable()
492 ret = val & mask ? 1 : 0; in _buck_get_suspend_enable()
526 uint mask = 0; in _ldo_get_enable() local
533 mask = 1 << (ldo - 4); in _ldo_get_enable()
536 mask = 1 << ldo; in _ldo_get_enable()
542 mask = 1 << ldo; in _ldo_get_enable()
550 mask = 1 << ldo; in _ldo_get_enable()
553 mask = 1 << (ldo - 4); in _ldo_get_enable()
556 mask = 1 << 0; in _ldo_get_enable()
567 return ret & mask ? true : false; in _ldo_get_enable()
573 uint mask, value, en_reg; in _ldo_set_enable() local
594 mask = 1 << ldo; in _ldo_set_enable()
595 ret = pmic_clrsetbits(pmic, REG_LDO_EN, mask, in _ldo_set_enable()
596 enable ? mask : 0); in _ldo_set_enable()
625 uint mask; in _ldo_set_suspend_enable() local
631 mask = 1 << ldo; in _ldo_set_suspend_enable()
632 ret = pmic_clrsetbits(pmic, RK816_REG_LDO_SLP_EN, mask, in _ldo_set_suspend_enable()
633 enable ? mask : 0); in _ldo_set_suspend_enable()
637 mask = 1 << ldo; in _ldo_set_suspend_enable()
638 ret = pmic_clrsetbits(pmic, REG_SLEEP_SET_OFF2, mask, in _ldo_set_suspend_enable()
639 enable ? 0 : mask); in _ldo_set_suspend_enable()
644 mask = 1 << 4; /* LDO9 */ in _ldo_set_suspend_enable()
645 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(0), mask, in _ldo_set_suspend_enable()
646 enable ? mask : 0); in _ldo_set_suspend_enable()
648 mask = 1 << ldo; in _ldo_set_suspend_enable()
649 ret = pmic_clrsetbits(pmic, RK817_POWER_SLP_EN(1), mask, in _ldo_set_suspend_enable()
650 enable ? mask : 0); in _ldo_set_suspend_enable()
662 uint mask; in _ldo_get_suspend_enable() local
667 mask = 1 << ldo; in _ldo_get_suspend_enable()
671 ret = val & mask ? 1 : 0; in _ldo_get_suspend_enable()
675 mask = 1 << ldo; in _ldo_get_suspend_enable()
679 ret = val & mask ? 0 : 1; in _ldo_get_suspend_enable()
684 mask = 1 << 4; /* LDO9 */ in _ldo_get_suspend_enable()
688 ret = val & mask ? 1 : 0; in _ldo_get_suspend_enable()
690 mask = 1 << ldo; in _ldo_get_suspend_enable()
694 ret = val & mask ? 1 : 0; in _ldo_get_suspend_enable()
707 int mask = info->vsel_mask; in buck_get_value() local
716 val = ret & mask; in buck_get_value()
733 int mask = info->vsel_mask; in buck_get_suspend_value() local
743 val = ret & mask; in buck_get_suspend_value()
787 int mask = info->vsel_mask; in ldo_get_value() local
795 val = ret & mask; in ldo_get_value()
804 int mask = info->vsel_mask; in ldo_set_value() local
816 __func__, uvolt, ldo + 1, info->vsel_reg, mask, val); in ldo_set_value()
818 return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val); in ldo_set_value()
825 int mask = info->vsel_mask; in ldo_set_suspend_value() local
837 __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val); in ldo_set_suspend_value()
839 return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val); in ldo_set_suspend_value()
846 int mask = info->vsel_mask; in ldo_get_suspend_value() local
856 val = ret & mask; in ldo_get_suspend_value()
893 uint mask = 0; in switch_set_enable() local
897 mask = 1 << (sw + 5); in switch_set_enable()
898 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, in switch_set_enable()
899 enable ? mask : 0); in switch_set_enable()
902 mask = (1 << (sw + 2)) | (1 << (sw + 6)); in switch_set_enable()
903 ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask, in switch_set_enable()
904 enable ? mask : 0); in switch_set_enable()
907 mask = 1 << 6; in switch_set_enable()
908 ret = pmic_clrsetbits(dev->parent, REG_DCDC_EN, mask, in switch_set_enable()
909 enable ? mask : 0); in switch_set_enable()
914 __func__, sw + 1, enable, mask); in switch_set_enable()
923 uint mask = 0; in switch_get_enable() local
927 mask = 1 << (sw + 5); in switch_get_enable()
931 mask = 1 << (sw + 2); in switch_get_enable()
935 mask = 1 << 6; in switch_get_enable()
943 return ret & mask ? true : false; in switch_get_enable()
960 uint mask = 0; in switch_set_suspend_enable() local
964 mask = 1 << (sw + 5); in switch_set_suspend_enable()
965 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, in switch_set_suspend_enable()
966 enable ? 0 : mask); in switch_set_suspend_enable()
969 mask = 1 << (sw + 6); in switch_set_suspend_enable()
970 ret = pmic_clrsetbits(dev->parent, RK817_POWER_SLP_EN(0), mask, in switch_set_suspend_enable()
971 enable ? mask : 0); in switch_set_suspend_enable()
974 mask = 1 << 6; in switch_set_suspend_enable()
975 ret = pmic_clrsetbits(dev->parent, REG_SLEEP_SET_OFF1, mask, in switch_set_suspend_enable()
976 enable ? 0 : mask); in switch_set_suspend_enable()
981 __func__, sw + 1, enable, mask); in switch_set_suspend_enable()
990 uint mask = 0; in switch_get_suspend_enable() local
994 mask = 1 << (sw + 5); in switch_get_suspend_enable()
998 ret = val & mask ? 0 : 1; in switch_get_suspend_enable()
1001 mask = 1 << (sw + 6); in switch_get_suspend_enable()
1005 ret = val & mask ? 1 : 0; in switch_get_suspend_enable()
1008 mask = 1 << 6; in switch_get_suspend_enable()
1012 ret = val & mask ? 0 : 1; in switch_get_suspend_enable()