Lines Matching refs:CPS_REG_WRITE
132 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval); in lpddr4_startsequencecontroller()
138 CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval); in lpddr4_startsequencecontroller()
249 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), in lpddr4_start()
326 CPS_REG_WRITE(lpddr4_addoffset in lpddr4_writereg()
335 CPS_REG_WRITE(lpddr4_addoffset in lpddr4_writereg()
344 CPS_REG_WRITE(lpddr4_addoffset in lpddr4_writereg()
412 CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval); in lpddr4_getmmrregister()
439 CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval); in lpddr4_writemmrregister()
676 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval); in lpddr4_setctlinterruptmask()
686 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval); in lpddr4_setctlinterruptmask()
750 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), in lpddr4_ackctlinterrupt()
754 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), in lpddr4_ackctlinterrupt()
805 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval); in lpddr4_setphyindepinterruptmask()
845 CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval); in lpddr4_ackphyindepinterrupt()
1112 CPS_REG_WRITE(regaddress, regval); in lpddr4_setphysnapsettings()
1138 CPS_REG_WRITE(regaddress, regval); in lpddr4_setphyadrsnapsettings()
1468 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), in writepdwakeup()
1477 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), in writepdwakeup()
1487 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), in writepdwakeup()
1506 CPS_REG_WRITE(& in writesrshortwakeup()
1516 CPS_REG_WRITE(& in writesrshortwakeup()
1527 CPS_REG_WRITE(& in writesrshortwakeup()
1547 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), in writesrlongwakeup()
1556 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), in writesrlongwakeup()
1566 CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), in writesrlongwakeup()
1585 CPS_REG_WRITE(& in writesrlonggatewakeup()
1596 CPS_REG_WRITE(& in writesrlonggatewakeup()
1608 CPS_REG_WRITE(& in writesrlonggatewakeup()
1629 CPS_REG_WRITE(& in writesrdpshortwakeup()
1639 CPS_REG_WRITE(& in writesrdpshortwakeup()
1650 CPS_REG_WRITE(& in writesrdpshortwakeup()
1670 CPS_REG_WRITE(& in writesrdplongwakeup()
1680 CPS_REG_WRITE(& in writesrdplongwakeup()
1691 CPS_REG_WRITE(& in writesrdplongwakeup()
1712 CPS_REG_WRITE(& in writesrdplonggatewakeup()
1724 CPS_REG_WRITE(& in writesrdplonggatewakeup()
1737 CPS_REG_WRITE(& in writesrdplonggatewakeup()
1849 CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval); in lpddr4_seteccenable()
1891 CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval); in lpddr4_setreducmode()
1986 CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval); in lpddr4_setdbimode()
2054 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), in lpddr4_setrefreshrate()
2064 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), in lpddr4_setrefreshrate()
2075 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), in lpddr4_setrefreshrate()
2101 CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), in lpddr4_refreshperchipselect()