Lines Matching refs:divide_roundup
2914 trp_value = divide_roundup(trp, tclk_psecs) - 1; in lmc_timing_params0()
2917 (unsigned int)(divide_roundup(max(4ull * tclk_psecs, 7500ull), in lmc_timing_params0()
2923 divide_roundup(max(4ull * tclk_psecs, 7500ull), in lmc_timing_params0()
2931 divide_roundup(max(5ull * tclk_psecs, trfc + 10000ull), in lmc_timing_params0()
2935 divide_roundup(max(5ull * tclk_psecs, 10000ull), tclk_psecs) - 1; in lmc_timing_params0()
2946 tp0.cn78xx.tzqcs = divide_roundup(128 * tclk_psecs, in lmc_timing_params0()
2949 divide_roundup(max(3 * tclk_psecs, (ulong)DDR3_TCKE), in lmc_timing_params0()
2952 divide_roundup((DDR4_TMRD * tclk_psecs), tclk_psecs) - 1; in lmc_timing_params0()
2954 tp0.cn78xx.tdllk = divide_roundup(DDR4_TDLLK, 256); in lmc_timing_params0()
2957 divide_roundup(max(512ull * tclk_psecs, 640000ull), in lmc_timing_params0()
2960 divide_roundup(max(64ull * tclk_psecs, DDR3_ZQCS), in lmc_timing_params0()
2962 tp0.cn78xx.tcke = divide_roundup(DDR3_TCKE, tclk_psecs) - 1; in lmc_timing_params0()
2964 divide_roundup((DDR3_TMRD * tclk_psecs), tclk_psecs) - 1; in lmc_timing_params0()
2966 divide_roundup(max(12ull * tclk_psecs, 15000ull), in lmc_timing_params0()
2968 tp0.cn78xx.tdllk = divide_roundup(DDR3_TDLLK, 256); in lmc_timing_params0()
2988 tp1.s.tmprr = divide_roundup(DDR3_TMPRR * tclk_psecs, tclk_psecs) - 1; in lmc_timing_params1()
2990 tp1.cn78xx.tras = divide_roundup(tras, tclk_psecs) - 1; in lmc_timing_params1()
2992 temp_trcd = divide_roundup(trcd, tclk_psecs); in lmc_timing_params1()
3008 tp1.cn78xx.twtr = divide_roundup(twtr, tclk_psecs) - 1; in lmc_timing_params1()
3009 tp1.cn78xx.trfc = divide_roundup(trfc, 8 * tclk_psecs); in lmc_timing_params1()
3014 divide_roundup(ddr4_trrd_lmin, tclk_psecs) - 2; in lmc_timing_params1()
3016 tp1.cn78xx.trrd = divide_roundup(trrd, tclk_psecs) - 2; in lmc_timing_params1()
3028 txp = divide_roundup(max((unsigned int)(3 * tclk_psecs), txp), in lmc_timing_params1()
3039 tp1.cn78xx.twlmrd = divide_roundup(DDR3_TWLMRD * tclk_psecs, in lmc_timing_params1()
3041 tp1.cn78xx.twldqsen = divide_roundup(DDR3_TWLDQSEN * tclk_psecs, in lmc_timing_params1()
3043 tp1.cn78xx.tfaw = divide_roundup(tfaw, 4 * tclk_psecs); in lmc_timing_params1()
3044 tp1.cn78xx.txpdll = divide_roundup(max(10ull * tclk_psecs, 24000ull), in lmc_timing_params1()
3067 divide_roundup(trfc_dlr * 1000UL, 8 * tclk_psecs); in lmc_timing_params1()
3094 temp_trrd_l = divide_roundup(ddr4_trrd_lmin, tclk_psecs) - 2; in lmc_timing_params2()
3107 tp2.s.trtp = divide_roundup(max(4ull * tclk_psecs, 7500ull), in lmc_timing_params2()
3265 param = divide_roundup(twr, tclk_psecs); in lmc_modereg_params0()
3546 mp3.s.tccd_l = max(divide_roundup(ddr4_tccd_lmin, tclk_psecs), in lmc_modereg_params3()
8119 cc2.cn78xx.ptune += divide_roundup(rl_comp_offs, 2); in lmc_read_leveling()
9496 cl = divide_roundup(taamin, tclk_psecs); in init_octeon3_ddr3_interface()