Lines Matching refs:dram
143 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
149 &dram->cru->softrst_con[1]); in rkclk_ddr_reset()
151 &dram->cru->softrst_con[2]); in rkclk_ddr_reset()
154 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
182 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); in rkclk_set_dpll()
184 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
186 &dram->cru->pll[1].con1); in rkclk_set_dpll()
190 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
195 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); in rkclk_set_dpll()
198 static void rkclk_configure_ddr(struct dram_info *dram, in rkclk_configure_ddr() argument
202 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHz * 2); in rkclk_configure_ddr()
247 static void set_ctl_address_map(struct dram_info *dram, in set_ctl_address_map() argument
251 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map()
306 int read_mr(struct dram_info *dram, u32 rank, u32 mr_num) in read_mr() argument
308 void __iomem *ddr_grf_base = dram->ddr_grf; in read_mr()
310 pctl_read_mr(dram->pctl, rank, mr_num); in read_mr()
317 static u32 check_rd_gate(struct dram_info *dram) in check_rd_gate() argument
319 void __iomem *phy_base = dram->phy; in check_rd_gate()
352 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype) in data_training() argument
354 void __iomem *pctl_base = dram->pctl; in data_training()
363 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); in data_training()
365 ret = phy_data_training(dram->phy, cs, dramtype); in data_training()
367 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); in data_training()
375 static void dram_set_bw(struct dram_info *dram, u32 bw) in dram_set_bw() argument
377 phy_dram_set_bw(dram->phy, bw); in dram_set_bw()
380 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) in set_ddrconfig() argument
382 writel(ddrconfig | (ddrconfig << 8), &dram->msch->deviceconf); in set_ddrconfig()
383 rk_clrsetreg(&dram->grf->soc_noc_con[1], 0x3 << 14, 0 << 14); in set_ddrconfig()
417 static void dram_all_config(struct dram_info *dram, in dram_all_config() argument
424 set_ddrconfig(dram, cap_info->ddrconfig); in dram_all_config()
427 writel(sys_reg2, &dram->pmugrf->os_reg[2]); in dram_all_config()
428 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in dram_all_config()
429 sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info, in dram_all_config()
433 static void enable_low_power(struct dram_info *dram, in enable_low_power() argument
436 void __iomem *pctl_base = dram->pctl; in enable_low_power()
437 void __iomem *phy_base = dram->phy; in enable_low_power()
438 void __iomem *ddr_grf_base = dram->ddr_grf; in enable_low_power()
450 writel(0x1f1f0617, &dram->ddr_grf->ddr_grf_con[1]); in enable_low_power()
485 static int sdram_init_(struct dram_info *dram, in sdram_init_() argument
489 void __iomem *pctl_base = dram->pctl; in sdram_init_()
491 rkclk_ddr_reset(dram, 1, 1, 1, 1); in sdram_init_()
498 rkclk_ddr_reset(dram, 1, 1, 1, 0); in sdram_init_()
499 rkclk_configure_ddr(dram, sdram_params); in sdram_init_()
502 rkclk_ddr_reset(dram, 1, 1, 0, 0); in sdram_init_()
504 phy_soft_reset(dram->phy); in sdram_init_()
506 rkclk_ddr_reset(dram, 1, 0, 0, 0); in sdram_init_()
507 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); in sdram_init_()
509 set_ctl_address_map(dram, sdram_params); in sdram_init_()
510 phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew, in sdram_init_()
516 rkclk_ddr_reset(dram, 0, 0, 0, 0); in sdram_init_()
522 pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3); in sdram_init_()
526 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { in sdram_init_()
531 if (check_rd_gate(dram)) { in sdram_init_()
537 if ((read_mr(dram, 1, 8) & 0x3) != 0x3) in sdram_init_()
540 if ((read_mr(dram, 1, 8) & 0x3) != 0x0) in sdram_init_()
546 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { in sdram_init_()
550 if (check_rd_gate(dram)) { in sdram_init_()
557 pctl_write_vrefdq(dram->pctl, 0x3, 5670, in sdram_init_()
560 dram_all_config(dram, sdram_params); in sdram_init_()
561 enable_low_power(dram, sdram_params); in sdram_init_()
566 static int dram_detect_cap(struct dram_info *dram, in dram_detect_cap() argument
619 if (data_training(dram, 1, dram_type) == 0) in dram_detect_cap()
625 dram_set_bw(dram, 2); in dram_detect_cap()
626 if (data_training(dram, 0, dram_type) == 0) in dram_detect_cap()
647 static int sdram_init_detect(struct dram_info *dram, in sdram_init_detect() argument
655 if (sdram_init_(dram, sdram_params, 0) != 0) in sdram_init_detect()
658 if (dram_detect_cap(dram, sdram_params, 0) != 0) in sdram_init_detect()
665 ret = sdram_init_(dram, sdram_params, 1); in sdram_init_detect()
672 sys_reg = readl(&dram->pmugrf->os_reg[2]); in sdram_init_detect()
673 sys_reg3 = readl(&dram->pmugrf->os_reg[3]); in sdram_init_detect()
676 writel(sys_reg, &dram->pmugrf->os_reg[2]); in sdram_init_detect()
677 writel(sys_reg3, &dram->pmugrf->os_reg[3]); in sdram_init_detect()