Lines Matching refs:sdram_params
199 struct px30_sdram_params *sdram_params) in rkclk_configure_ddr() argument
202 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHz * 2); in rkclk_configure_ddr()
210 static unsigned int calculate_ddrconfig(struct px30_sdram_params *sdram_params) in calculate_ddrconfig() argument
212 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in calculate_ddrconfig()
222 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
248 struct px30_sdram_params *sdram_params) in set_ctl_address_map() argument
250 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in set_ctl_address_map()
255 if (sdram_params->base.dramtype == DDR4) in set_ctl_address_map()
272 if (sdram_params->base.dramtype == DDR4) { in set_ctl_address_map()
294 if ((sdram_params->base.dramtype == LPDDR3 || in set_ctl_address_map()
295 sdram_params->base.dramtype == LPDDR2) && in set_ctl_address_map()
298 if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) in set_ctl_address_map()
418 struct px30_sdram_params *sdram_params) in dram_all_config() argument
420 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_all_config()
425 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, in dram_all_config()
429 sdram_msch_config(dram->msch, &sdram_params->ch.noc_timings, cap_info, in dram_all_config()
430 &sdram_params->base); in dram_all_config()
434 struct px30_sdram_params *sdram_params) in enable_low_power() argument
452 if (sdram_params->base.dramtype == DDR4) in enable_low_power()
454 else if (sdram_params->base.dramtype == DDR3) in enable_low_power()
486 struct px30_sdram_params *sdram_params, u32 pre_init) in sdram_init_() argument
488 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init_()
499 rkclk_configure_ddr(dram, sdram_params); in sdram_init_()
507 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE); in sdram_init_()
508 cap_info->ddrconfig = calculate_ddrconfig(sdram_params); in sdram_init_()
509 set_ctl_address_map(dram, sdram_params); in sdram_init_()
510 phy_cfg(dram->phy, &sdram_params->phy_regs, sdram_params->skew, in sdram_init_()
511 &sdram_params->base, cap_info->bw); in sdram_init_()
521 if (sdram_params->base.dramtype == LPDDR3) in sdram_init_()
526 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { in sdram_init_()
536 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init_()
539 } else if (sdram_params->base.dramtype == LPDDR2) { in sdram_init_()
546 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { in sdram_init_()
556 if (sdram_params->base.dramtype == DDR4) in sdram_init_()
558 sdram_params->base.dramtype); in sdram_init_()
560 dram_all_config(dram, sdram_params); in sdram_init_()
561 enable_low_power(dram, sdram_params); in sdram_init_()
567 struct px30_sdram_params *sdram_params, in dram_detect_cap() argument
570 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in dram_detect_cap()
583 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap()
648 struct px30_sdram_params *sdram_params) in sdram_init_detect() argument
650 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; in sdram_init_detect()
655 if (sdram_init_(dram, sdram_params, 0) != 0) in sdram_init_detect()
658 if (dram_detect_cap(dram, sdram_params, 0) != 0) in sdram_init_detect()
662 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, in sdram_init_detect()
663 sdram_params->base.dramtype); in sdram_init_detect()
665 ret = sdram_init_(dram, sdram_params, 1); in sdram_init_detect()
670 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); in sdram_init_detect()
697 struct px30_sdram_params *sdram_params; in sdram_init() local
708 sdram_params = get_default_sdram_config(); in sdram_init()
709 ret = sdram_init_detect(&dram_info, sdram_params); in sdram_init()
714 sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base); in sdram_init()