Lines Matching refs:sdram_params
231 struct rk3188_sdram_params *sdram_params, in pctl_cfg() argument
234 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
235 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
236 switch (sdram_params->base.dramtype) { in pctl_cfg()
238 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
239 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
242 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
245 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
260 struct rk3188_sdram_params *sdram_params) in phy_cfg() argument
264 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
270 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
271 sizeof(sdram_params->phy_timing)); in phy_cfg()
272 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
284 switch (sdram_params->base.dramtype) { in phy_cfg()
291 if (sdram_params->base.odt) { in phy_cfg()
419 struct rk3188_sdram_params *sdram_params) in data_training() argument
432 if (sdram_params->base.dramtype != LPDDR3) in data_training()
434 rank = sdram_params->ch[channel].rank | 1; in data_training()
472 if (sdram_params->base.dramtype != LPDDR3) in data_training()
476 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
523 struct rk3188_sdram_params *sdram_params) in dram_cfg_rbc() argument
527 if (sdram_params->ch[chnum].bk == 3) in dram_cfg_rbc()
533 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
537 struct rk3188_sdram_params *sdram_params) in dram_all_config() argument
542 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
543 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; in dram_all_config()
544 for (chan = 0; chan < sdram_params->num_channels; chan++) { in dram_all_config()
546 &sdram_params->ch[chan]; in dram_all_config()
558 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
560 if (sdram_params->ch[0].rank == 2) in dram_all_config()
569 struct rk3188_sdram_params *sdram_params) in sdram_rank_bw_detect() argument
578 if (data_training(chan, channel, sdram_params) < 0) { in sdram_rank_bw_detect()
589 sdram_params->ch[channel].rank = 1; in sdram_rank_bw_detect()
591 sdram_params->ch[channel].rank << 18); in sdram_rank_bw_detect()
596 sdram_params->ch[channel].bw = 1; in sdram_rank_bw_detect()
598 sdram_params->ch[channel].bw, in sdram_rank_bw_detect()
604 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
607 (data_training(chan, channel, sdram_params) < 0)) { in sdram_rank_bw_detect()
608 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
630 struct rk3188_sdram_params *sdram_params) in sdram_col_row_detect() argument
643 (1 << (col + sdram_params->ch[channel].bw - 1)); in sdram_col_row_detect()
654 sdram_params->ch[channel].col = col; in sdram_col_row_detect()
674 sdram_params->ch[channel].cs1_row = row; in sdram_col_row_detect()
675 sdram_params->ch[channel].row_3_4 = 0; in sdram_col_row_detect()
677 sdram_params->ch[channel].cs0_row = row; in sdram_col_row_detect()
684 static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params) in sdram_get_niu_config() argument
688 row = sdram_params->ch[0].cs0_row; in sdram_get_niu_config()
695 tmp = sdram_params->ch[0].col - 9; in sdram_get_niu_config()
696 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; in sdram_get_niu_config()
707 sdram_params->base.ddrconfig = i; in sdram_get_niu_config()
714 struct rk3188_sdram_params *sdram_params) in sdram_init() argument
720 if ((sdram_params->base.dramtype == DDR3 && in sdram_init()
721 sdram_params->base.ddr_freq > 800000000)) { in sdram_init()
726 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
738 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
740 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
742 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
744 phy_cfg(chan, channel, sdram_params); in sdram_init()
752 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
756 sdram_params->ch[channel].bw = 2; in sdram_init()
758 sdram_params->ch[channel].bw, dram->grf); in sdram_init()
765 sdram_params->ch[channel].rank = 2, in sdram_init()
767 (sdram_params->ch[channel].rank | 1) << 18); in sdram_init()
778 sdram_rank_bw_detect(dram, channel, sdram_params); in sdram_init()
780 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
789 sdram_params->ch[channel].bk = 3; in sdram_init()
791 ret = sdram_col_row_detect(dram, channel, sdram_params); in sdram_init()
796 ret = sdram_get_niu_config(sdram_params); in sdram_init()
800 dram_all_config(dram, sdram_params); in sdram_init()