Lines Matching refs:ddr_phy
93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
123 void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) in phy_dll_bypass_set() argument
127 setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10); in phy_dll_bypass_set()
128 setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10); in phy_dll_bypass_set()
129 setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10); in phy_dll_bypass_set()
130 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10); in phy_dll_bypass_set()
131 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10); in phy_dll_bypass_set()
133 clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8); in phy_dll_bypass_set()
134 clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8); in phy_dll_bypass_set()
135 clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8); in phy_dll_bypass_set()
136 clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8); in phy_dll_bypass_set()
137 clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8); in phy_dll_bypass_set()
140 setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); in phy_dll_bypass_set()
142 clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f); in phy_dll_bypass_set()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
237 u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf; in data_training()
244 clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30, in data_training()
246 setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); in data_training()
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
251 clrbits_le32(&ddr_phy->ddrphy_reg[2], in data_training()
367 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset() local
371 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); in phy_softreset()
373 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); in phy_softreset()
375 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); in phy_softreset()
383 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw() local
388 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4); in set_bw()
390 clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); in set_bw()
391 clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); in set_bw()
394 setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4); in set_bw()
397 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8); in set_bw()
398 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8); in set_bw()
473 struct rk322x_ddr_phy *ddr_phy = chan->phy; in phy_cfg() local
488 writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); in phy_cfg()
491 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); in phy_cfg()
494 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]); in phy_cfg()
498 writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]); in phy_cfg()
499 writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]); in phy_cfg()
509 writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]); in phy_cfg()
510 clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3); in phy_cfg()
511 writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]); in phy_cfg()
512 writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]); in phy_cfg()
514 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]); in phy_cfg()
515 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]); in phy_cfg()
516 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]); in phy_cfg()
517 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]); in phy_cfg()
518 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]); in phy_cfg()
519 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]); in phy_cfg()
520 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]); in phy_cfg()
521 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]); in phy_cfg()
523 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]); in phy_cfg()
524 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]); in phy_cfg()
525 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]); in phy_cfg()
526 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]); in phy_cfg()
527 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]); in phy_cfg()
528 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]); in phy_cfg()
529 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]); in phy_cfg()
530 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]); in phy_cfg()