Lines Matching refs:sdram_params
165 struct rk322x_sdram_params *sdram_params) in memory_init() argument
168 u32 dramtype = sdram_params->base.dramtype; in memory_init()
176 (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
181 (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
186 (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
191 ((sdram_params->phy_timing.mr[0] | in memory_init()
214 (sdram_params->phy_timing.mr[1] & in memory_init()
218 (sdram_params->phy_timing.mr[2] & in memory_init()
222 (sdram_params->phy_timing.mr[3] & in memory_init()
227 (sdram_params->phy_timing.mr11 & in memory_init()
403 struct rk322x_sdram_params *sdram_params, in pctl_cfg() argument
408 u32 dramtype = sdram_params->base.dramtype; in pctl_cfg()
410 if (sdram_params->ch[0].bw == 2) in pctl_cfg()
425 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
440 if (sdram_params->phy_timing.bl & PHT_BL_8) in pctl_cfg()
471 struct rk322x_sdram_params *sdram_params) in phy_cfg() argument
475 struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing; in phy_cfg()
476 struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing; in phy_cfg()
477 struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing; in phy_cfg()
486 switch (sdram_params->base.dramtype) { in phy_cfg()
504 if (sdram_params->base.dramtype == LPDDR2) in phy_cfg()
534 struct rk322x_sdram_params *sdram_params) in dram_cfg_rbc() argument
538 struct rk322x_sdram_channel *config = &sdram_params->ch[0]; in dram_cfg_rbc()
580 struct rk322x_sdram_params *sdram_params) in dram_all_config() argument
582 struct rk322x_sdram_channel *info = &sdram_params->ch[0]; in dram_all_config()
585 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
603 struct rk322x_sdram_params *sdram_params) in dram_cap_detect() argument
609 if (sdram_params->base.dramtype == DDR3) in dram_cap_detect()
610 sdram_params->ch[0].dbw = 1; in dram_cap_detect()
612 sdram_params->ch[0].dbw = 2; in dram_cap_detect()
630 sdram_params->ch[0].bw = bw; in dram_cap_detect()
631 sdram_params->ch[0].bk = 3; in dram_cap_detect()
652 sdram_params->ch[0].col = col; in dram_cap_detect()
670 sdram_params->ch[0].cs1_row = row; in dram_cap_detect()
671 sdram_params->ch[0].row_3_4 = 0; in dram_cap_detect()
672 sdram_params->ch[0].cs0_row = row; in dram_cap_detect()
680 sdram_params->ch[0].rank = 2; in dram_cap_detect()
682 sdram_params->ch[0].rank = 1; in dram_cap_detect()
688 struct rk322x_sdram_params *sdram_params) in sdram_init() argument
693 sdram_params->base.ddr_freq * MHz * 2); in sdram_init()
700 phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq); in sdram_init()
701 pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf); in sdram_init()
702 phy_cfg(&dram->chan[0], sdram_params); in sdram_init()
706 memory_init(&dram->chan[0], sdram_params); in sdram_init()
708 ret = dram_cap_detect(dram, sdram_params); in sdram_init()
711 dram_cfg_rbc(&dram->chan[0], sdram_params); in sdram_init()
712 dram_all_config(dram, sdram_params); in sdram_init()