Lines Matching refs:sdram_params
245 struct rk3288_sdram_params *sdram_params, in pctl_cfg() argument
250 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; in pctl_cfg()
251 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
252 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
253 switch (sdram_params->base.dramtype) { in pctl_cfg()
255 writel(sdram_params->pctl_timing.tcl - 1, in pctl_cfg()
257 writel(sdram_params->pctl_timing.tcwl, in pctl_cfg()
268 sdram_params->base.odt); in pctl_cfg()
271 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
272 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
275 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
278 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
295 struct rk3288_sdram_params *sdram_params) in phy_cfg() argument
299 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
305 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
306 sizeof(sdram_params->phy_timing)); in phy_cfg()
307 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
309 writel(sdram_params->base.noc_activate, &msch->activate); in phy_cfg()
322 switch (sdram_params->base.dramtype) { in phy_cfg()
350 if (sdram_params->base.odt) { in phy_cfg()
478 struct rk3288_sdram_params *sdram_params) in data_training() argument
491 if (sdram_params->base.dramtype != LPDDR3) in data_training()
493 rank = sdram_params->ch[channel].rank | 1; in data_training()
531 if (sdram_params->base.dramtype != LPDDR3) in data_training()
535 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
581 struct rk3288_sdram_params *sdram_params) in dram_cfg_rbc() argument
585 if (sdram_params->ch[chnum].bk == 3) in dram_cfg_rbc()
591 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
595 struct rk3288_sdram_params *sdram_params) in dram_all_config() argument
600 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
601 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; in dram_all_config()
602 for (chan = 0; chan < sdram_params->num_channels; chan++) { in dram_all_config()
604 &sdram_params->ch[chan]; in dram_all_config()
616 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
619 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
623 struct rk3288_sdram_params *sdram_params) in sdram_rank_bw_detect() argument
630 if (data_training(chan, channel, sdram_params) < 0) { in sdram_rank_bw_detect()
638 sdram_params->num_channels = 1; in sdram_rank_bw_detect()
643 sdram_params->ch[channel].rank = 1; in sdram_rank_bw_detect()
645 sdram_params->ch[channel].rank << 18); in sdram_rank_bw_detect()
650 sdram_params->ch[channel].bw = 1; in sdram_rank_bw_detect()
652 sdram_params->ch[channel].bw, in sdram_rank_bw_detect()
658 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
661 (data_training(chan, channel, sdram_params) < 0)) { in sdram_rank_bw_detect()
662 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
676 struct rk3288_sdram_params *sdram_params) in sdram_col_row_detect() argument
689 (1 << (col + sdram_params->ch[channel].bw - 1)); in sdram_col_row_detect()
700 sdram_params->ch[channel].col = col; in sdram_col_row_detect()
719 sdram_params->ch[channel].cs1_row = row; in sdram_col_row_detect()
720 sdram_params->ch[channel].row_3_4 = 0; in sdram_col_row_detect()
722 sdram_params->ch[channel].cs0_row = row; in sdram_col_row_detect()
729 static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params) in sdram_get_niu_config() argument
733 tmp = sdram_params->ch[0].col - 9; in sdram_get_niu_config()
734 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; in sdram_get_niu_config()
735 tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4); in sdram_get_niu_config()
744 sdram_params->base.ddrconfig = i; in sdram_get_niu_config()
750 static int sdram_get_stride(struct rk3288_sdram_params *sdram_params) in sdram_get_stride() argument
754 long cap = sdram_params->num_channels * (1u << in sdram_get_stride()
755 (sdram_params->ch[0].cs0_row + in sdram_get_stride()
756 sdram_params->ch[0].col + in sdram_get_stride()
757 (sdram_params->ch[0].rank - 1) + in sdram_get_stride()
758 sdram_params->ch[0].bw + in sdram_get_stride()
780 sdram_params->base.stride = stride; in sdram_get_stride()
786 struct rk3288_sdram_params *sdram_params) in sdram_init() argument
793 if ((sdram_params->base.dramtype == DDR3 && in sdram_init()
794 sdram_params->base.ddr_freq > 800000000) || in sdram_init()
795 (sdram_params->base.dramtype == LPDDR3 && in sdram_init()
796 sdram_params->base.ddr_freq > 533000000)) { in sdram_init()
802 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
820 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
822 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
824 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
826 phy_cfg(chan, channel, sdram_params); in sdram_init()
834 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
837 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
845 sdram_params->phy_timing.mr[1]); in sdram_init()
848 sdram_params->phy_timing.mr[2]); in sdram_init()
851 sdram_params->phy_timing.mr[3]); in sdram_init()
856 sdram_params->ch[channel].bw = 2; in sdram_init()
858 sdram_params->ch[channel].bw, dram->grf); in sdram_init()
865 sdram_params->ch[channel].rank = 2, in sdram_init()
867 (sdram_params->ch[channel].rank | 1) << 18); in sdram_init()
876 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
880 sdram_params->ch[channel].rank | 1, in sdram_init()
882 sdram_params->base.odt ? 3 : 0); in sdram_init()
895 sdram_rank_bw_detect(dram, channel, sdram_params); in sdram_init()
897 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
906 sdram_params->ch[channel].bk = 3; in sdram_init()
908 ret = sdram_col_row_detect(dram, channel, sdram_params); in sdram_init()
913 ret = sdram_get_niu_config(sdram_params); in sdram_init()
917 ret = sdram_get_stride(sdram_params); in sdram_init()
921 dram_all_config(dram, sdram_params); in sdram_init()