Lines Matching defs:stm32_fmc_regs
25 struct stm32_fmc_regs { struct
27 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
28 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
29 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
30 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
31 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
32 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
33 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
34 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
35 u32 reserved1[24];
38 u32 pcr; /* NAND Flash control register */
39 u32 sr; /* FIFO status and interrupt register */
40 u32 pmem; /* Common memory space timing register */
41 u32 patt; /* Attribute memory space timing registers */
42 u32 reserved2[1];
43 u32 eccr; /* ECC result registers */
44 u32 reserved3[27];
47 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
48 u32 reserved4[1];
49 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
50 u32 reserved5[1];
51 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
52 u32 reserved6[1];
53 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
54 u32 reserved7[8];
57 u32 sdcr1; /* SDRAM Control register 1 */
58 u32 sdcr2; /* SDRAM Control register 2 */
59 u32 sdtr1; /* SDRAM Timing register 1 */
60 u32 sdtr2; /* SDRAM Timing register 2 */
61 u32 sdcmr; /* SDRAM Mode register */
62 u32 sdrtr; /* SDRAM Refresh timing register */
63 u32 sdsr; /* SDRAM Status register */