Lines Matching refs:tx_slot
91 uint tx_slot; member
172 priv->tx_slot = 0; in bcmstb_spi_probe()
209 debug("WR ENDQP: %d\n", priv->tx_slot - 1); in bcmstb_spi_submit()
210 writel(priv->tx_slot - 1, &priv->regs->endqp); in bcmstb_spi_submit()
213 debug("WR CDRAM[%d]: %02x\n", priv->tx_slot - 1, in bcmstb_spi_submit()
214 readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80); in bcmstb_spi_submit()
215 writel(readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80, in bcmstb_spi_submit()
216 &priv->regs->cdram[priv->tx_slot - 1]); in bcmstb_spi_submit()
305 priv->tx_slot = 0; in bcmstb_spi_xfer()
350 priv->rx_slot = priv->tx_slot; in bcmstb_spi_xfer()
352 while (priv->tx_slot < NUM_CDRAM && tx_len > 0) { in bcmstb_spi_xfer()
354 debug("WR TXRAM[%d]: %02x\n", priv->tx_slot, in bcmstb_spi_xfer()
357 ®s->txram[priv->tx_slot << 1]); in bcmstb_spi_xfer()
358 debug("WR CDRAM[%d]: %02x\n", priv->tx_slot, 0x8e); in bcmstb_spi_xfer()
359 writel(0x8e, ®s->cdram[priv->tx_slot]); in bcmstb_spi_xfer()
360 priv->tx_slot++; in bcmstb_spi_xfer()
383 priv->tx_slot %= NUM_CDRAM; in bcmstb_spi_xfer()