Lines Matching refs:CQSPI_REG_CONFIG
59 #define CQSPI_REG_CONFIG 0x00 macro
170 ((readl(base + CQSPI_REG_CONFIG) >> \
184 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
186 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
192 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
194 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
201 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_dac_mode_enable()
203 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_dac_mode_enable()
264 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
282 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
292 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
300 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
315 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
334 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
799 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()
803 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()