Lines Matching refs:reg_base
173 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ argument
174 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
177 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ argument
178 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
181 void cadence_qspi_apb_controller_enable(void *reg_base) in cadence_qspi_apb_controller_enable() argument
184 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
186 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
189 void cadence_qspi_apb_controller_disable(void *reg_base) in cadence_qspi_apb_controller_disable() argument
192 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
194 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
197 void cadence_qspi_apb_dac_mode_enable(void *reg_base) in cadence_qspi_apb_dac_mode_enable() argument
201 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_dac_mode_enable()
203 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_dac_mode_enable()
207 static unsigned int cadence_qspi_wait_idle(void *reg_base) in cadence_qspi_wait_idle() argument
215 if (CQSPI_REG_IS_IDLE(reg_base)) in cadence_qspi_wait_idle()
233 void cadence_qspi_apb_readdata_capture(void *reg_base, in cadence_qspi_apb_readdata_capture() argument
237 cadence_qspi_apb_controller_disable(reg_base); in cadence_qspi_apb_readdata_capture()
239 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE); in cadence_qspi_apb_readdata_capture()
252 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE); in cadence_qspi_apb_readdata_capture()
254 cadence_qspi_apb_controller_enable(reg_base); in cadence_qspi_apb_readdata_capture()
257 void cadence_qspi_apb_config_baudrate_div(void *reg_base, in cadence_qspi_apb_config_baudrate_div() argument
263 cadence_qspi_apb_controller_disable(reg_base); in cadence_qspi_apb_config_baudrate_div()
264 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
282 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()
284 cadence_qspi_apb_controller_enable(reg_base); in cadence_qspi_apb_config_baudrate_div()
287 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) in cadence_qspi_apb_set_clk_mode() argument
291 cadence_qspi_apb_controller_disable(reg_base); in cadence_qspi_apb_set_clk_mode()
292 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
300 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()
302 cadence_qspi_apb_controller_enable(reg_base); in cadence_qspi_apb_set_clk_mode()
305 void cadence_qspi_apb_chipselect(void *reg_base, in cadence_qspi_apb_chipselect() argument
310 cadence_qspi_apb_controller_disable(reg_base); in cadence_qspi_apb_chipselect()
315 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
334 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_chipselect()
336 cadence_qspi_apb_controller_enable(reg_base); in cadence_qspi_apb_chipselect()
339 void cadence_qspi_apb_delay(void *reg_base, in cadence_qspi_apb_delay() argument
349 cadence_qspi_apb_controller_disable(reg_base); in cadence_qspi_apb_delay()
375 writel(reg, reg_base + CQSPI_REG_DELAY); in cadence_qspi_apb_delay()
377 cadence_qspi_apb_controller_enable(reg_base); in cadence_qspi_apb_delay()
407 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, in cadence_qspi_apb_exec_flash_cmd() argument
413 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cadence_qspi_apb_exec_flash_cmd()
416 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cadence_qspi_apb_exec_flash_cmd()
419 reg = readl(reg_base + CQSPI_REG_CMDCTRL); in cadence_qspi_apb_exec_flash_cmd()
431 if (!cadence_qspi_wait_idle(reg_base)) in cadence_qspi_apb_exec_flash_cmd()
438 int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op) in cadence_qspi_apb_command_read() argument
458 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); in cadence_qspi_apb_command_read()
462 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); in cadence_qspi_apb_command_read()
470 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); in cadence_qspi_apb_command_read()
479 int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op) in cadence_qspi_apb_command_write() argument
512 writel(wr_data, reg_base + in cadence_qspi_apb_command_write()
519 writel(wr_data, reg_base + in cadence_qspi_apb_command_write()
525 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg); in cadence_qspi_apb_command_write()
794 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) in cadence_qspi_apb_enter_xip() argument
799 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()
803 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_enter_xip()
806 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT); in cadence_qspi_apb_enter_xip()
809 reg = readl(reg_base + CQSPI_REG_RD_INSTR); in cadence_qspi_apb_enter_xip()
811 writel(reg, reg_base + CQSPI_REG_RD_INSTR); in cadence_qspi_apb_enter_xip()