zynq_spi.c - OpenGrok cross reference for /u-boot/drivers/spi/zynq

Lines Matching refs:confr
96 	u32 confr;  in zynq_spi_init_hw()  local
99 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;  in zynq_spi_init_hw()
100 	writel(~confr, &regs->enr);  in zynq_spi_init_hw()
114 	confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |  in zynq_spi_init_hw()
116 	confr &= ~ZYNQ_SPI_CR_MSA_MASK;  in zynq_spi_init_hw()
117 	writel(confr, &regs->cr);  in zynq_spi_init_hw()
224 	u32 confr;  in zynq_spi_release_bus()  local
226 	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;  in zynq_spi_release_bus()
227 	writel(~confr, &regs->enr);  in zynq_spi_release_bus()
303 	uint32_t confr;  in zynq_spi_set_speed()  local
310 	confr = readl(&regs->cr);  in zynq_spi_set_speed()
321 	confr &= ~ZYNQ_SPI_CR_BAUD_MASK;  in zynq_spi_set_speed()
322 	confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);  in zynq_spi_set_speed()
324 	writel(confr, &regs->cr);  in zynq_spi_set_speed()
337 	uint32_t confr;  in zynq_spi_set_mode()  local
340 	confr = readl(&regs->cr);  in zynq_spi_set_mode()
341 	confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);  in zynq_spi_set_mode()
344 		confr |= ZYNQ_SPI_CR_CPHA_MASK;  in zynq_spi_set_mode()
346 		confr |= ZYNQ_SPI_CR_CPOL_MASK;  in zynq_spi_set_mode()
348 	writel(confr, &regs->cr);  in zynq_spi_set_mode()