Lines Matching refs:xceiv
349 switch (musb->xceiv->state) { in musb_otg_timer_func()
353 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_otg_timer_func()
359 otg_state_string(musb->xceiv->state)); in musb_otg_timer_func()
361 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; in musb_otg_timer_func()
365 otg_state_string(musb->xceiv->state)); in musb_otg_timer_func()
380 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
382 switch (musb->xceiv->state) { in musb_hnp_stop()
386 otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
391 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_hnp_stop()
400 otg_state_string(musb->xceiv->state)); in musb_hnp_stop()
428 struct usb_otg *otg = musb->xceiv->otg; in musb_stage0_irq()
442 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
447 switch (musb->xceiv->state) { in musb_stage0_irq()
470 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
475 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
482 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
485 switch (musb->xceiv->state) { in musb_stage0_irq()
488 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
511 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
527 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
538 musb->xceiv->state = OTG_STATE_A_IDLE; in musb_stage0_irq()
564 switch (musb->xceiv->state) { in musb_stage0_irq()
592 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
617 otg_state_string(musb->xceiv->state), devctl, power); in musb_stage0_irq()
620 switch (musb->xceiv->state) { in musb_stage0_irq()
645 musb->xceiv->state = OTG_STATE_B_WAIT_ACON; in musb_stage0_irq()
658 musb->xceiv->state = OTG_STATE_A_SUSPEND; in musb_stage0_irq()
702 switch (musb->xceiv->state) { in musb_stage0_irq()
714 musb->xceiv->state = OTG_STATE_B_HOST; in musb_stage0_irq()
722 musb->xceiv->state = OTG_STATE_A_HOST; in musb_stage0_irq()
736 otg_state_string(musb->xceiv->state), devctl); in musb_stage0_irq()
743 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
747 switch (musb->xceiv->state) { in musb_stage0_irq()
764 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
780 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
806 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
807 switch (musb->xceiv->state) { in musb_stage0_irq()
819 otg_state_string(musb->xceiv->state), in musb_stage0_irq()
831 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
832 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
836 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; in musb_stage0_irq()
843 otg_state_string(musb->xceiv->state)); in musb_stage0_irq()
1704 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); in musb_mode_show()
1749 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) in musb_vbus_store()
1821 if (musb->xceiv->state != old_state) { in musb_irq_work()
1822 old_state = musb->xceiv->state; in musb_irq_work()
1985 if (!musb->xceiv->io_ops) { in musb_init_controller()
1986 musb->xceiv->io_dev = musb->controller; in musb_init_controller()
1987 musb->xceiv->io_priv = musb->mregs; in musb_init_controller()
1988 musb->xceiv->io_ops = &musb_ulpi_access; in musb_init_controller()
2046 otg_set_host(musb->xceiv->otg, &hcd->self); in musb_init_controller()
2050 musb->xceiv->otg->host = &hcd->self; in musb_init_controller()
2071 musb->xceiv->otg->default_a = 1; in musb_init_controller()
2072 musb->xceiv->state = OTG_STATE_A_IDLE; in musb_init_controller()
2088 musb->xceiv->otg->default_a = 0; in musb_init_controller()
2089 musb->xceiv->state = OTG_STATE_B_IDLE; in musb_init_controller()