Lines Matching refs:csr
42 u16 csr; in write_toggle() local
45 csr = readw(&musbr->txcsr); in write_toggle()
47 if (csr & MUSB_TXCSR_MODE) in write_toggle()
48 csr = MUSB_TXCSR_CLRDATATOG; in write_toggle()
50 csr = 0; in write_toggle()
51 writew(csr, &musbr->txcsr); in write_toggle()
53 csr |= MUSB_TXCSR_H_WR_DATATOGGLE; in write_toggle()
54 writew(csr, &musbr->txcsr); in write_toggle()
55 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); in write_toggle()
56 writew(csr, &musbr->txcsr); in write_toggle()
60 csr = readw(&musbr->txcsr); in write_toggle()
61 if (csr & MUSB_TXCSR_MODE) in write_toggle()
62 csr = MUSB_RXCSR_CLRDATATOG; in write_toggle()
64 csr = 0; in write_toggle()
65 writew(csr, &musbr->rxcsr); in write_toggle()
67 csr = readw(&musbr->rxcsr); in write_toggle()
68 csr |= MUSB_RXCSR_H_WR_DATATOGGLE; in write_toggle()
69 writew(csr, &musbr->rxcsr); in write_toggle()
70 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); in write_toggle()
71 writew(csr, &musbr->rxcsr); in write_toggle()
83 u16 csr; in check_stall() local
87 csr = readw(&musbr->txcsr); in check_stall()
88 if (csr & MUSB_CSR0_H_RXSTALL) { in check_stall()
89 csr &= ~MUSB_CSR0_H_RXSTALL; in check_stall()
90 writew(csr, &musbr->txcsr); in check_stall()
95 csr = readw(&musbr->txcsr); in check_stall()
96 if (csr & MUSB_TXCSR_H_RXSTALL) { in check_stall()
97 csr &= ~MUSB_TXCSR_H_RXSTALL; in check_stall()
98 writew(csr, &musbr->txcsr); in check_stall()
102 csr = readw(&musbr->rxcsr); in check_stall()
103 if (csr & MUSB_RXCSR_H_RXSTALL) { in check_stall()
104 csr &= ~MUSB_RXCSR_H_RXSTALL; in check_stall()
105 writew(csr, &musbr->rxcsr); in check_stall()
119 u16 csr; in wait_until_ep0_ready() local
124 csr = readw(&musbr->txcsr); in wait_until_ep0_ready()
125 if (csr & MUSB_CSR0_H_ERROR) { in wait_until_ep0_ready()
126 csr &= ~MUSB_CSR0_H_ERROR; in wait_until_ep0_ready()
127 writew(csr, &musbr->txcsr); in wait_until_ep0_ready()
135 if (!(csr & MUSB_CSR0_TXPKTRDY)) { in wait_until_ep0_ready()
149 if (csr & MUSB_CSR0_RXPKTRDY) in wait_until_ep0_ready()
154 if (!(csr & MUSB_CSR0_H_REQPKT)) { in wait_until_ep0_ready()
182 u16 csr; in wait_until_txep_ready() local
191 csr = readw(&musbr->txcsr); in wait_until_txep_ready()
192 if (csr & MUSB_TXCSR_H_ERROR) { in wait_until_txep_ready()
205 } while (csr & MUSB_TXCSR_TXPKTRDY); in wait_until_txep_ready()
214 u16 csr; in wait_until_rxep_ready() local
223 csr = readw(&musbr->rxcsr); in wait_until_rxep_ready()
224 if (csr & MUSB_RXCSR_H_ERROR) { in wait_until_rxep_ready()
237 } while (!(csr & MUSB_RXCSR_RXPKTRDY)); in wait_until_rxep_ready()
247 u16 csr; in ctrlreq_setup_phase() local
253 csr = readw(&musbr->txcsr); in ctrlreq_setup_phase()
254 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); in ctrlreq_setup_phase()
255 writew(csr, &musbr->txcsr); in ctrlreq_setup_phase()
268 u16 csr; in ctrlreq_in_data_phase() local
281 csr = readw(&musbr->txcsr); in ctrlreq_in_data_phase()
282 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); in ctrlreq_in_data_phase()
294 csr = readw(&musbr->txcsr); in ctrlreq_in_data_phase()
295 csr &= ~MUSB_CSR0_RXPKTRDY; in ctrlreq_in_data_phase()
296 writew(csr, &musbr->txcsr); in ctrlreq_in_data_phase()
314 u16 csr; in ctrlreq_out_data_phase() local
329 csr = readw(&musbr->txcsr); in ctrlreq_out_data_phase()
331 csr |= MUSB_CSR0_TXPKTRDY; in ctrlreq_out_data_phase()
332 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_out_data_phase()
333 writew(csr, &musbr->txcsr); in ctrlreq_out_data_phase()
349 u16 csr; in ctrlreq_out_status_phase() local
353 csr = readw(&musbr->txcsr); in ctrlreq_out_status_phase()
354 csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_out_status_phase()
355 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_out_status_phase()
356 writew(csr, &musbr->txcsr); in ctrlreq_out_status_phase()
368 u16 csr; in ctrlreq_in_status_phase() local
372 csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; in ctrlreq_in_status_phase()
373 csr |= MUSB_CSR0_H_DIS_PING; in ctrlreq_in_status_phase()
374 writew(csr, &musbr->txcsr); in ctrlreq_in_status_phase()
378 csr = readw(&musbr->txcsr); in ctrlreq_in_status_phase()
379 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); in ctrlreq_in_status_phase()
380 writew(csr, &musbr->txcsr); in ctrlreq_in_status_phase()
856 u16 csr; in submit_bulk_msg() local
916 csr = readw(&musbr->txcsr); in submit_bulk_msg()
917 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); in submit_bulk_msg()
923 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); in submit_bulk_msg()
931 csr = readw(&musbr->txcsr); in submit_bulk_msg()
933 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); in submit_bulk_msg()
951 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
952 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); in submit_bulk_msg()
956 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
958 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_bulk_msg()
959 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_bulk_msg()
960 writew(csr, &musbr->rxcsr); in submit_bulk_msg()
970 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
971 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_bulk_msg()
972 writew(csr, &musbr->rxcsr); in submit_bulk_msg()
977 csr = readw(&musbr->rxcsr); in submit_bulk_msg()
979 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_bulk_msg()
1063 u16 csr; in submit_int_msg() local
1124 csr = readw(&musbr->rxcsr); in submit_int_msg()
1125 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); in submit_int_msg()
1129 csr = readw(&musbr->rxcsr); in submit_int_msg()
1131 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_int_msg()
1132 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_int_msg()
1133 writew(csr, &musbr->rxcsr); in submit_int_msg()
1143 csr = readw(&musbr->rxcsr); in submit_int_msg()
1144 csr &= ~MUSB_RXCSR_RXPKTRDY; in submit_int_msg()
1145 writew(csr, &musbr->rxcsr); in submit_int_msg()
1150 csr = readw(&musbr->rxcsr); in submit_int_msg()
1152 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); in submit_int_msg()