Lines Matching refs:reg32
362 u32 reg32; in igd_setup_panel() local
365 reg32 = (plat->dp_hotplug[0] & 0x7) << 2; in igd_setup_panel()
366 reg32 |= (plat->dp_hotplug[1] & 0x7) << 10; in igd_setup_panel()
367 reg32 |= (plat->dp_hotplug[2] & 0x7) << 18; in igd_setup_panel()
368 gtt_write(priv, PCH_PORT_HOTPLUG, reg32); in igd_setup_panel()
371 reg32 = (plat->port_select & 0x3) << 30; in igd_setup_panel()
372 reg32 |= (plat->power_up_delay & 0x1fff) << 16; in igd_setup_panel()
373 reg32 |= (plat->power_backlight_on_delay & 0x1fff); in igd_setup_panel()
374 gtt_write(priv, PCH_PP_ON_DELAYS, reg32); in igd_setup_panel()
377 reg32 = (plat->power_down_delay & 0x1fff) << 16; in igd_setup_panel()
378 reg32 |= (plat->power_backlight_off_delay & 0x1fff); in igd_setup_panel()
379 gtt_write(priv, PCH_PP_OFF_DELAYS, reg32); in igd_setup_panel()
383 reg32 = gtt_read(priv, PCH_PP_DIVISOR); in igd_setup_panel()
384 reg32 &= ~0xff; in igd_setup_panel()
385 reg32 |= plat->power_cycle_delay & 0xff; in igd_setup_panel()
386 gtt_write(priv, PCH_PP_DIVISOR, reg32); in igd_setup_panel()