Lines Matching refs:lcdc_write
166 static inline void lcdc_write(unsigned int val, u32 *addr) in lcdc_write() function
227 lcdc_write(LCD_CLK_MAIN_RESET, in lcd_enable_raster()
233 lcdc_write(0, in lcd_enable_raster()
240 lcdc_write(reg | LCD_RASTER_ENABLE, in lcd_enable_raster()
257 lcdc_write(reg & ~LCD_RASTER_ENABLE, in lcd_disable_raster()
271 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcd_disable_raster()
273 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); in lcd_disable_raster()
307 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
312 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
313 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
314 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
315 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
318 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
319 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
320 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
321 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
334 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
337 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
338 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
341 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); in lcd_blit()
342 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcd_blit()
376 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); in lcd_cfg_dma()
389 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_ac_bias()
401 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_horizontal_sync()
413 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_vertical_sync()
452 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_cfg_display()
455 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_display()
479 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_display()
512 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_frame_buffer()
518 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_frame_buffer()
524 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_frame_buffer()
538 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_frame_buffer()
637 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); in lcd_reset()
638 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); in lcd_reset()
641 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); in lcd_reset()
643 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
644 lcdc_write(0, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
660 lcdc_write(LCD_CLK_DIVISOR(div) | in lcd_calc_clk_divider()
664 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | in lcd_calc_clk_divider()
681 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | in lcd_init()
685 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & in lcd_init()
724 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | in lcd_init()
733 lcdc_write(par->dma_start, in lcdc_dma_start()
735 lcdc_write(par->dma_end, in lcdc_dma_start()
737 lcdc_write(0, in lcdc_dma_start()
739 lcdc_write(0, in lcdc_dma_start()
752 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
765 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
770 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcdc_irq_handler_rev01()
776 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
781 lcdc_write(par->dma_start, in lcdc_irq_handler_rev01()
783 lcdc_write(par->dma_end, in lcdc_irq_handler_rev01()
800 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
802 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
814 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
819 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); in lcdc_irq_handler_rev02()
823 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
826 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
831 lcdc_write(par->dma_start, in lcdc_irq_handler_rev02()
833 lcdc_write(par->dma_end, in lcdc_irq_handler_rev02()
836 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
839 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
1015 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); in video_hw_init()
1017 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); in video_hw_init()