Lines Matching refs:dsi
266 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) in dsi_write() argument
268 writel(val, dsi->base + reg); in dsi_write()
271 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) in dsi_read() argument
273 return readl(dsi->base + reg); in dsi_read()
279 struct dw_mipi_dsi *dsi = host_to_dsi(host); in dw_mipi_dsi_host_attach() local
281 if (device->lanes > dsi->max_data_lanes) { in dw_mipi_dsi_host_attach()
288 dsi->channel = device->channel; in dw_mipi_dsi_host_attach()
293 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, in dw_mipi_message_config() argument
304 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); in dw_mipi_message_config()
305 dsi_write(dsi, DSI_CMD_MODE_CFG, val); in dw_mipi_message_config()
308 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) in dw_mipi_dsi_gen_pkt_hdr_write() argument
313 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_gen_pkt_hdr_write()
317 dev_err(dsi->dsi_host.dev, in dw_mipi_dsi_gen_pkt_hdr_write()
322 dsi_write(dsi, DSI_GEN_HDR, hdr_val); in dw_mipi_dsi_gen_pkt_hdr_write()
325 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_gen_pkt_hdr_write()
329 dev_err(dsi->dsi_host.dev, "failed to write command FIFO\n"); in dw_mipi_dsi_gen_pkt_hdr_write()
336 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_write() argument
348 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); in dw_mipi_dsi_write()
352 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); in dw_mipi_dsi_write()
357 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_write()
361 dev_err(dsi->dsi_host.dev, in dw_mipi_dsi_write()
369 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); in dw_mipi_dsi_write()
372 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_read() argument
380 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_read()
384 dev_err(dsi->dsi_host.dev, "Timeout during read operation\n"); in dw_mipi_dsi_read()
390 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_read()
394 dev_err(dsi->dsi_host.dev, in dw_mipi_dsi_read()
399 val = dsi_read(dsi, DSI_GEN_PLD_DATA); in dw_mipi_dsi_read()
410 struct dw_mipi_dsi *dsi = host_to_dsi(host); in dw_mipi_dsi_host_transfer() local
420 dw_mipi_message_config(dsi, msg); in dw_mipi_dsi_host_transfer()
422 ret = dw_mipi_dsi_write(dsi, &packet); in dw_mipi_dsi_host_transfer()
427 ret = dw_mipi_dsi_read(dsi, msg); in dw_mipi_dsi_host_transfer()
443 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_video_mode_config() argument
445 struct mipi_dsi_device *device = dsi->device; in dw_mipi_dsi_video_mode_config()
462 dsi_write(dsi, DSI_VID_MODE_CFG, val); in dw_mipi_dsi_video_mode_config()
465 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_set_mode() argument
468 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; in dw_mipi_dsi_set_mode()
470 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_set_mode()
473 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); in dw_mipi_dsi_set_mode()
474 dw_mipi_dsi_video_mode_config(dsi); in dw_mipi_dsi_set_mode()
475 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); in dw_mipi_dsi_set_mode()
477 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); in dw_mipi_dsi_set_mode()
481 phy_ops->post_set_mode(dsi->device, mode_flags); in dw_mipi_dsi_set_mode()
483 dsi_write(dsi, DSI_PWR_UP, POWERUP); in dw_mipi_dsi_set_mode()
486 static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_init_pll() argument
488 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; in dw_mipi_dsi_init_pll()
497 phy_ops->get_esc_clk_rate(dsi->device, &esc_rate); in dw_mipi_dsi_init_pll()
508 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; in dw_mipi_dsi_init_pll()
510 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_init_pll()
517 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | in dw_mipi_dsi_init_pll()
521 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_dpi_config() argument
524 struct mipi_dsi_device *device = dsi->device; in dw_mipi_dsi_dpi_config()
547 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); in dw_mipi_dsi_dpi_config()
548 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); in dw_mipi_dsi_dpi_config()
549 dsi_write(dsi, DSI_DPI_CFG_POL, val); in dw_mipi_dsi_dpi_config()
556 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) in dw_mipi_dsi_dpi_config()
560 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_packet_handler_config() argument
562 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN); in dw_mipi_dsi_packet_handler_config()
565 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_video_packet_config() argument
575 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ)); in dw_mipi_dsi_video_packet_config()
578 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_command_mode_config() argument
580 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; in dw_mipi_dsi_command_mode_config()
587 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); in dw_mipi_dsi_command_mode_config()
593 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); in dw_mipi_dsi_command_mode_config()
594 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); in dw_mipi_dsi_command_mode_config()
597 phy_ops->post_set_mode(dsi->device, 0); in dw_mipi_dsi_command_mode_config()
601 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_get_hcomponent_lbcc() argument
607 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; in dw_mipi_dsi_get_hcomponent_lbcc()
617 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_line_timer_config() argument
632 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal); in dw_mipi_dsi_line_timer_config()
633 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
635 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa); in dw_mipi_dsi_line_timer_config()
636 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
638 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp); in dw_mipi_dsi_line_timer_config()
639 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
642 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_vertical_timing_config() argument
652 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); in dw_mipi_dsi_vertical_timing_config()
653 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); in dw_mipi_dsi_vertical_timing_config()
654 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); in dw_mipi_dsi_vertical_timing_config()
655 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); in dw_mipi_dsi_vertical_timing_config()
658 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_dphy_timing_config() argument
660 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; in dw_mipi_dsi_dphy_timing_config()
665 phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing); in dw_mipi_dsi_dphy_timing_config()
675 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; in dw_mipi_dsi_dphy_timing_config()
678 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) | in dw_mipi_dsi_dphy_timing_config()
680 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); in dw_mipi_dsi_dphy_timing_config()
682 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) | in dw_mipi_dsi_dphy_timing_config()
686 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp) in dw_mipi_dsi_dphy_timing_config()
690 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_dphy_interface_config() argument
692 struct mipi_dsi_device *device = dsi->device; in dw_mipi_dsi_dphy_interface_config()
699 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | in dw_mipi_dsi_dphy_interface_config()
703 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_dphy_init() argument
706 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK in dw_mipi_dsi_dphy_init()
708 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); in dw_mipi_dsi_dphy_init()
709 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); in dw_mipi_dsi_dphy_init()
710 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); in dw_mipi_dsi_dphy_init()
713 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_dphy_enable() argument
718 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | in dw_mipi_dsi_dphy_enable()
721 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, in dw_mipi_dsi_dphy_enable()
724 dev_dbg(dsi->dsi_host.dev, in dw_mipi_dsi_dphy_enable()
727 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, in dw_mipi_dsi_dphy_enable()
731 dev_dbg(dsi->dsi_host.dev, in dw_mipi_dsi_dphy_enable()
735 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_clear_err() argument
737 dsi_read(dsi, DSI_INT_ST0); in dw_mipi_dsi_clear_err()
738 dsi_read(dsi, DSI_INT_ST1); in dw_mipi_dsi_clear_err()
739 dsi_write(dsi, DSI_INT_MSK0, 0); in dw_mipi_dsi_clear_err()
740 dsi_write(dsi, DSI_INT_MSK1, 0); in dw_mipi_dsi_clear_err()
743 static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_bridge_set() argument
746 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops; in dw_mipi_dsi_bridge_set()
747 struct mipi_dsi_device *device = dsi->device; in dw_mipi_dsi_bridge_set()
750 ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes, in dw_mipi_dsi_bridge_set()
751 device->format, &dsi->lane_mbps); in dw_mipi_dsi_bridge_set()
753 dev_warn(dsi->dsi_host.dev, "Phy get_lane_mbps() failed\n"); in dw_mipi_dsi_bridge_set()
755 dw_mipi_dsi_init_pll(dsi); in dw_mipi_dsi_bridge_set()
756 dw_mipi_dsi_dpi_config(dsi, timings); in dw_mipi_dsi_bridge_set()
757 dw_mipi_dsi_packet_handler_config(dsi); in dw_mipi_dsi_bridge_set()
758 dw_mipi_dsi_video_mode_config(dsi); in dw_mipi_dsi_bridge_set()
759 dw_mipi_dsi_video_packet_config(dsi, timings); in dw_mipi_dsi_bridge_set()
760 dw_mipi_dsi_command_mode_config(dsi); in dw_mipi_dsi_bridge_set()
761 dw_mipi_dsi_line_timer_config(dsi, timings); in dw_mipi_dsi_bridge_set()
762 dw_mipi_dsi_vertical_timing_config(dsi, timings); in dw_mipi_dsi_bridge_set()
764 dw_mipi_dsi_dphy_init(dsi); in dw_mipi_dsi_bridge_set()
765 dw_mipi_dsi_dphy_timing_config(dsi); in dw_mipi_dsi_bridge_set()
766 dw_mipi_dsi_dphy_interface_config(dsi); in dw_mipi_dsi_bridge_set()
768 dw_mipi_dsi_clear_err(dsi); in dw_mipi_dsi_bridge_set()
770 ret = phy_ops->init(dsi->device); in dw_mipi_dsi_bridge_set()
772 dev_warn(dsi->dsi_host.dev, "Phy init() failed\n"); in dw_mipi_dsi_bridge_set()
774 dw_mipi_dsi_dphy_enable(dsi); in dw_mipi_dsi_bridge_set()
779 dw_mipi_dsi_set_mode(dsi, 0); in dw_mipi_dsi_bridge_set()
788 struct dw_mipi_dsi *dsi = dev_get_priv(dev); in dw_mipi_dsi_init() local
797 dsi->phy_ops = phy_ops; in dw_mipi_dsi_init()
798 dsi->max_data_lanes = max_data_lanes; in dw_mipi_dsi_init()
799 dsi->device = device; in dw_mipi_dsi_init()
800 dsi->dsi_host.dev = (struct device *)dev; in dw_mipi_dsi_init()
801 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; in dw_mipi_dsi_init()
802 device->host = &dsi->dsi_host; in dw_mipi_dsi_init()
804 dsi->base = (void *)dev_read_addr(device->dev); in dw_mipi_dsi_init()
805 if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) { in dw_mipi_dsi_init()
819 dw_mipi_dsi_bridge_set(dsi, timings); in dw_mipi_dsi_init()
826 struct dw_mipi_dsi *dsi = dev_get_priv(dev); in dw_mipi_dsi_enable() local
829 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); in dw_mipi_dsi_enable()