Lines Matching refs:dsim
53 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, in exynos_mipi_dsi_long_data_wr() argument
94 exynos_mipi_dsi_wr_tx_data(dsim, payload); in exynos_mipi_dsi_long_data_wr()
98 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, in exynos_mipi_dsi_wr_data() argument
105 if (dsim->state == DSIM_STATE_ULPS) { in exynos_mipi_dsi_wr_data()
111 delay_val = MHZ / dsim->dsim_config->esc_clk; in exynos_mipi_dsi_wr_data()
117 if (dsim->state == DSIM_STATE_STOP) { in exynos_mipi_dsi_wr_data()
118 while (!(exynos_mipi_dsi_get_fifo_state(dsim) & in exynos_mipi_dsi_wr_data()
139 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); in exynos_mipi_dsi_wr_data()
152 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); in exynos_mipi_dsi_wr_data()
173 exynos_mipi_dsi_clear_all_interrupt(dsim); in exynos_mipi_dsi_wr_data()
174 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); in exynos_mipi_dsi_wr_data()
193 exynos_mipi_dsi_wr_tx_data(dsim, payload); in exynos_mipi_dsi_wr_data()
200 exynos_mipi_dsi_long_data_wr(dsim, data0, data1); in exynos_mipi_dsi_wr_data()
204 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff, in exynos_mipi_dsi_wr_data()
235 int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable) in exynos_mipi_dsi_pll_on() argument
242 exynos_mipi_dsi_clear_interrupt(dsim); in exynos_mipi_dsi_pll_on()
243 exynos_mipi_dsi_enable_pll(dsim, 1); in exynos_mipi_dsi_pll_on()
246 if (exynos_mipi_dsi_is_pll_stable(dsim)) in exynos_mipi_dsi_pll_on()
252 exynos_mipi_dsi_enable_pll(dsim, 0); in exynos_mipi_dsi_pll_on()
257 unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim, in exynos_mipi_dsi_change_pll() argument
288 exynos_mipi_dsi_enable_afc(dsim, 0, 0); in exynos_mipi_dsi_change_pll()
291 exynos_mipi_dsi_enable_afc(dsim, 1, 0x1); in exynos_mipi_dsi_change_pll()
293 exynos_mipi_dsi_enable_afc(dsim, 1, 0x0); in exynos_mipi_dsi_change_pll()
295 exynos_mipi_dsi_enable_afc(dsim, 1, 0x3); in exynos_mipi_dsi_change_pll()
297 exynos_mipi_dsi_enable_afc(dsim, 1, 0x2); in exynos_mipi_dsi_change_pll()
299 exynos_mipi_dsi_enable_afc(dsim, 1, 0x5); in exynos_mipi_dsi_change_pll()
301 exynos_mipi_dsi_enable_afc(dsim, 1, 0x4); in exynos_mipi_dsi_change_pll()
323 exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler); in exynos_mipi_dsi_change_pll()
325 exynos_mipi_dsi_hs_zero_ctrl(dsim, 0); in exynos_mipi_dsi_change_pll()
326 exynos_mipi_dsi_prep_ctrl(dsim, 0); in exynos_mipi_dsi_change_pll()
329 exynos_mipi_dsi_pll_freq_band(dsim, freq_band); in exynos_mipi_dsi_change_pll()
332 exynos_mipi_dsi_pll_stable_time(dsim, in exynos_mipi_dsi_change_pll()
333 dsim->dsim_config->pll_stable_time); in exynos_mipi_dsi_change_pll()
342 int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim, in exynos_mipi_dsi_set_clock() argument
350 dsim->e_clk_src = byte_clk_sel; in exynos_mipi_dsi_set_clock()
353 exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel); in exynos_mipi_dsi_set_clock()
357 hs_clk = exynos_mipi_dsi_change_pll(dsim, in exynos_mipi_dsi_set_clock()
358 dsim->dsim_config->p, dsim->dsim_config->m, in exynos_mipi_dsi_set_clock()
359 dsim->dsim_config->s); in exynos_mipi_dsi_set_clock()
366 exynos_mipi_dsi_enable_pll_bypass(dsim, 0); in exynos_mipi_dsi_set_clock()
367 exynos_mipi_dsi_pll_on(dsim, 1); in exynos_mipi_dsi_set_clock()
375 esc_div = byte_clk / (dsim->dsim_config->esc_clk); in exynos_mipi_dsi_set_clock()
377 esc_div, byte_clk, dsim->dsim_config->esc_clk); in exynos_mipi_dsi_set_clock()
379 (byte_clk / esc_div) > dsim->dsim_config->esc_clk) in exynos_mipi_dsi_set_clock()
387 exynos_mipi_dsi_enable_byte_clock(dsim, 1); in exynos_mipi_dsi_set_clock()
390 exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div); in exynos_mipi_dsi_set_clock()
392 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim, in exynos_mipi_dsi_set_clock()
393 (DSIM_LANE_CLOCK | dsim->data_lane), 1); in exynos_mipi_dsi_set_clock()
398 (dsim->dsim_config->esc_clk / MHZ)); in exynos_mipi_dsi_set_clock()
415 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim, in exynos_mipi_dsi_set_clock()
416 (DSIM_LANE_CLOCK | dsim->data_lane), 0); in exynos_mipi_dsi_set_clock()
417 exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0); in exynos_mipi_dsi_set_clock()
420 exynos_mipi_dsi_enable_byte_clock(dsim, 0); in exynos_mipi_dsi_set_clock()
423 exynos_mipi_dsi_pll_on(dsim, 0); in exynos_mipi_dsi_set_clock()
429 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim) in exynos_mipi_dsi_init_dsim() argument
431 dsim->state = DSIM_STATE_INIT; in exynos_mipi_dsi_init_dsim()
433 switch (dsim->dsim_config->e_no_data_lane) { in exynos_mipi_dsi_init_dsim()
435 dsim->data_lane = DSIM_LANE_DATA0; in exynos_mipi_dsi_init_dsim()
438 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1; in exynos_mipi_dsi_init_dsim()
441 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | in exynos_mipi_dsi_init_dsim()
445 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | in exynos_mipi_dsi_init_dsim()
453 exynos_mipi_dsi_sw_reset(dsim); in exynos_mipi_dsi_init_dsim()
454 exynos_mipi_dsi_dp_dn_swap(dsim, 0); in exynos_mipi_dsi_init_dsim()
459 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim, in exynos_mipi_dsi_enable_frame_done_int() argument
463 exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable); in exynos_mipi_dsi_enable_frame_done_int()
481 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim, in exynos_mipi_dsi_set_display_mode() argument
488 dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd; in exynos_mipi_dsi_set_display_mode()
494 if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) { in exynos_mipi_dsi_set_display_mode()
495 if (dsim->dsim_config->auto_vertical_cnt == 0) { in exynos_mipi_dsi_set_display_mode()
496 exynos_mipi_dsi_set_main_disp_vporch(dsim, in exynos_mipi_dsi_set_display_mode()
500 exynos_mipi_dsi_set_main_disp_hporch(dsim, in exynos_mipi_dsi_set_display_mode()
503 exynos_mipi_dsi_set_main_disp_sync_area(dsim, in exynos_mipi_dsi_set_display_mode()
509 exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres, in exynos_mipi_dsi_set_display_mode()
512 exynos_mipi_dsi_display_config(dsim, dsim->dsim_config); in exynos_mipi_dsi_set_display_mode()
520 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim) in exynos_mipi_dsi_init_link() argument
524 switch (dsim->state) { in exynos_mipi_dsi_init_link()
526 exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f); in exynos_mipi_dsi_init_link()
529 exynos_mipi_dsi_init_config(dsim); in exynos_mipi_dsi_init_link()
530 exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1); in exynos_mipi_dsi_init_link()
531 exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1); in exynos_mipi_dsi_init_link()
534 exynos_mipi_dsi_set_clock(dsim, in exynos_mipi_dsi_init_link()
535 dsim->dsim_config->e_byte_clk, 1); in exynos_mipi_dsi_init_link()
538 while (!(exynos_mipi_dsi_is_lane_state(dsim))) { in exynos_mipi_dsi_init_link()
548 dsim->state = DSIM_STATE_STOP; in exynos_mipi_dsi_init_link()
551 exynos_mipi_dsi_set_stop_state_counter(dsim, in exynos_mipi_dsi_init_link()
552 dsim->dsim_config->stop_holding_cnt); in exynos_mipi_dsi_init_link()
553 exynos_mipi_dsi_set_bta_timeout(dsim, in exynos_mipi_dsi_init_link()
554 dsim->dsim_config->bta_timeout); in exynos_mipi_dsi_init_link()
555 exynos_mipi_dsi_set_lpdr_timeout(dsim, in exynos_mipi_dsi_init_link()
556 dsim->dsim_config->rx_timeout); in exynos_mipi_dsi_init_link()
567 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim) in exynos_mipi_dsi_set_hs_enable() argument
569 if (dsim->state == DSIM_STATE_STOP) { in exynos_mipi_dsi_set_hs_enable()
570 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) { in exynos_mipi_dsi_set_hs_enable()
571 dsim->state = DSIM_STATE_HSCLKEN; in exynos_mipi_dsi_set_hs_enable()
574 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); in exynos_mipi_dsi_set_hs_enable()
575 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0); in exynos_mipi_dsi_set_hs_enable()
577 exynos_mipi_dsi_enable_hs_clock(dsim, 1); in exynos_mipi_dsi_set_hs_enable()
588 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim, in exynos_mipi_dsi_set_data_transfer_mode() argument
592 if (dsim->state != DSIM_STATE_HSCLKEN) { in exynos_mipi_dsi_set_data_transfer_mode()
597 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); in exynos_mipi_dsi_set_data_transfer_mode()
599 if (dsim->state == DSIM_STATE_INIT || dsim->state == in exynos_mipi_dsi_set_data_transfer_mode()
605 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0); in exynos_mipi_dsi_set_data_transfer_mode()
611 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim) in exynos_mipi_dsi_get_frame_done_status() argument
613 return _exynos_mipi_dsi_get_frame_done_status(dsim); in exynos_mipi_dsi_get_frame_done_status()
616 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) in exynos_mipi_dsi_clear_frame_done() argument
618 _exynos_mipi_dsi_clear_frame_done(dsim); in exynos_mipi_dsi_clear_frame_done()