Lines Matching refs:hdmi
48 struct dw_hdmi hdmi; member
67 static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr) in dw_hdmi_top_read() argument
69 struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi, in dw_hdmi_top_read()
70 hdmi); in dw_hdmi_top_read()
74 return readl(hdmi->ioaddr + in dw_hdmi_top_read()
78 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
79 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
82 data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
83 data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
88 static inline void dw_hdmi_top_write(struct dw_hdmi *hdmi, in dw_hdmi_top_write() argument
91 struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi, in dw_hdmi_top_write()
92 hdmi); in dw_hdmi_top_write()
95 writel(data, hdmi->ioaddr + in dw_hdmi_top_write()
101 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
102 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
105 writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_write()
108 static inline void dw_hdmi_top_write_bits(struct dw_hdmi *hdmi, in dw_hdmi_top_write_bits() argument
113 unsigned int data = dw_hdmi_top_read(hdmi, addr); in dw_hdmi_top_write_bits()
117 dw_hdmi_top_write(hdmi, addr, data); in dw_hdmi_top_write_bits()
120 static u8 dw_hdmi_dwc_read(struct dw_hdmi *hdmi, int addr) in dw_hdmi_dwc_read() argument
125 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
126 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
129 data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_read()
130 data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_read()
135 static inline void dw_hdmi_dwc_write(struct dw_hdmi *hdmi, u8 data, int addr) in dw_hdmi_dwc_write() argument
138 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
139 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
142 writel(data, hdmi->ioaddr + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_write()
145 static inline void dw_hdmi_dwc_write_bits(struct dw_hdmi *hdmi, in dw_hdmi_dwc_write_bits() argument
150 u8 data = dw_hdmi_dwc_read(hdmi, addr); in dw_hdmi_dwc_write_bits()
155 dw_hdmi_dwc_write(hdmi, data, addr); in dw_hdmi_dwc_write_bits()
188 ret = dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); in meson_dw_hdmi_read_edid()
295 static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock) in meson_dw_hdmi_phy_init() argument
297 struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi, in meson_dw_hdmi_phy_init()
298 hdmi); in meson_dw_hdmi_phy_init()
306 dw_hdmi_top_write(hdmi, HDMITX_TOP_SW_RESET, 0); in meson_dw_hdmi_phy_init()
309 dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3); in meson_dw_hdmi_phy_init()
310 dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4); in meson_dw_hdmi_phy_init()
313 dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); in meson_dw_hdmi_phy_init()
316 dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f); in meson_dw_hdmi_phy_init()
317 dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f); in meson_dw_hdmi_phy_init()
320 dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); in meson_dw_hdmi_phy_init()
322 dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); in meson_dw_hdmi_phy_init()
359 return dw_hdmi_enable(&priv->hdmi, edid); in meson_dw_hdmi_enable()
362 static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi) in meson_dw_hdmi_wait_hpd() argument
368 if (dw_hdmi_top_read(hdmi, HDMITX_TOP_STAT0)) in meson_dw_hdmi_wait_hpd()
389 priv->hdmi.ioaddr = (ulong)dev_remap_addr_index(dev, 0); in meson_dw_hdmi_probe()
390 if (!priv->hdmi.ioaddr) in meson_dw_hdmi_probe()
397 priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; in meson_dw_hdmi_probe()
398 priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24; in meson_dw_hdmi_probe()
399 priv->hdmi.phy_set = meson_dw_hdmi_phy_init; in meson_dw_hdmi_probe()
401 priv->hdmi.reg_io_width = 1; in meson_dw_hdmi_probe()
403 priv->hdmi.write_reg = dw_hdmi_dwc_write; in meson_dw_hdmi_probe()
404 priv->hdmi.read_reg = dw_hdmi_dwc_read; in meson_dw_hdmi_probe()
406 priv->hdmi.i2c_clk_high = 0x67; in meson_dw_hdmi_probe()
407 priv->hdmi.i2c_clk_low = 0x78; in meson_dw_hdmi_probe()
424 &priv->hdmi.ddc_bus); in meson_dw_hdmi_probe()
460 priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG); in meson_dw_hdmi_probe()
462 priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG); in meson_dw_hdmi_probe()
466 dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_SW_RESET, 0); in meson_dw_hdmi_probe()
468 dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_CLK_CNTL, 0xff); in meson_dw_hdmi_probe()
470 dw_hdmi_init(&priv->hdmi); in meson_dw_hdmi_probe()
471 dw_hdmi_phy_init(&priv->hdmi); in meson_dw_hdmi_probe()
474 ret = meson_dw_hdmi_wait_hpd(&priv->hdmi); in meson_dw_hdmi_probe()