Lines Matching refs:_REG
67 priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
70 priv->io_base + _REG(VPP_OSD_SCI_WH_M1)); in meson_vpp_setup_interlace_vscaler_osd1()
73 priv->io_base + _REG(VPP_OSD_SCO_H_START_END)); in meson_vpp_setup_interlace_vscaler_osd1()
75 priv->io_base + _REG(VPP_OSD_SCO_V_START_END)); in meson_vpp_setup_interlace_vscaler_osd1()
78 writel(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE)); in meson_vpp_setup_interlace_vscaler_osd1()
79 writel(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP)); in meson_vpp_setup_interlace_vscaler_osd1()
81 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
90 priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpp_setup_interlace_vscaler_osd1()
96 writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
97 writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
98 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_vpp_disable_interlace_vscaler_osd1()
120 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_vpu_setup_plane()
125 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_vpu_setup_plane()
129 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_vpu_setup_plane()
132 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_vpu_setup_plane()
135 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_vpu_setup_plane()
139 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_vpu_setup_plane()
142 priv->io_base + _REG(VPP_MISC)); in meson_vpu_setup_plane()
161 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_vpu_setup_plane()
183 writel(osd1_ctrl_stat, priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_vpu_setup_plane()
184 writel(osd1_blk0_cfg[0], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); in meson_vpu_setup_plane()
185 writel(osd1_blk0_cfg[1], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1)); in meson_vpu_setup_plane()
186 writel(osd1_blk0_cfg[2], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2)); in meson_vpu_setup_plane()
187 writel(osd1_blk0_cfg[3], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3)); in meson_vpu_setup_plane()
188 writel(osd1_blk0_cfg[4], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4)); in meson_vpu_setup_plane()
204 priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_H)); in meson_vpu_setup_plane()
206 priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_V)); in meson_vpu_setup_plane()
208 priv->io_base + _REG(VIU_OSD_BLEND_BLEND0_SIZE)); in meson_vpu_setup_plane()
210 priv->io_base + _REG(VIU_OSD_BLEND_BLEND1_SIZE)); in meson_vpu_setup_plane()
212 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_vpu_setup_plane()
215 priv->io_base + _REG(VPP_MISC)); in meson_vpu_setup_plane()