Lines Matching refs:_REG
31 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
53 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
56 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
78 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
81 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
127 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
129 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
131 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
133 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
135 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
137 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
139 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
142 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
144 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
147 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
157 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_osd_matrix()
159 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_osd_matrix()
161 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01)); in meson_viu_set_osd_matrix()
163 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10)); in meson_viu_set_osd_matrix()
165 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12)); in meson_viu_set_osd_matrix()
167 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21)); in meson_viu_set_osd_matrix()
172 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
175 _REG(VIU_OSD1_MATRIX_COEF31_32)); in meson_viu_set_osd_matrix()
178 _REG(VIU_OSD1_MATRIX_COEF40_41)); in meson_viu_set_osd_matrix()
180 _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
183 _REG(VIU_OSD1_MATRIX_COEF22_30)); in meson_viu_set_osd_matrix()
187 priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_osd_matrix()
189 priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2)); in meson_viu_set_osd_matrix()
193 _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
196 _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
200 priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); in meson_viu_set_osd_matrix()
202 priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); in meson_viu_set_osd_matrix()
210 _REG(VIU_OSD1_EOTF_CTL + i + 1)); in meson_viu_set_osd_matrix()
213 priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); in meson_viu_set_osd_matrix()
215 priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); in meson_viu_set_osd_matrix()
246 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
250 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
253 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
257 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
261 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
264 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
268 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
271 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
273 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
277 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
280 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
284 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
288 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
291 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
295 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
298 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
301 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
378 writel(reg, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); in meson_vpu_init()
382 writel(reg, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); in meson_vpu_init()
387 writel(reg, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); in meson_vpu_init()
391 writel(reg, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); in meson_vpu_init()
403 writel(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_vpu_init()
411 priv->io_base + _REG(VPU_HDMI_SETTING)); in meson_vpu_init()
414 writel(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_vpu_init()
415 writel(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_vpu_init()
416 writel(0, priv->io_base + _REG(ENCL_VIDEO_EN)); in meson_vpu_init()
419 writel(0, priv->io_base + _REG(VENC_INTCTRL)); in meson_vpu_init()
423 writel(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpu_init()
426 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpu_init()
428 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpu_init()
430 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpu_init()
432 writel(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpu_init()
437 priv->io_base + _REG(VPP_OFIFO_SIZE)); in meson_vpu_init()
440 priv->io_base + _REG(VPP_OFIFO_SIZE)); in meson_vpu_init()
442 priv->io_base + _REG(VPP_HOLD_LINES)); in meson_vpu_init()
447 priv->io_base + _REG(VPP_MISC)); in meson_vpu_init()
451 priv->io_base + _REG(VPP_MISC)); in meson_vpu_init()
457 priv->io_base + _REG(VPP_MISC)); in meson_vpu_init()
461 priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END)); in meson_vpu_init()
463 priv->io_base + _REG(VPP_BLEND_VD2_H_START_END)); in meson_vpu_init()
467 writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpu_init()
468 writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpu_init()
469 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_vpu_init()
473 priv->io_base + _REG(VPP_SC_MISC)); in meson_vpu_init()
477 priv->io_base + _REG(VPP_VADJ_CTRL)); in meson_vpu_init()
493 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_vpu_init()
495 priv->io_base + _REG(VIU_OSD2_CTRL_STAT)); in meson_vpu_init()
517 writel(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); in meson_vpu_init()
518 writel(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); in meson_vpu_init()
523 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_vpu_init()
526 priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); in meson_vpu_init()
531 priv->io_base + _REG(VIU_MISC_CTRL0)); in meson_vpu_init()
532 writel(0, priv->io_base + _REG(AFBC_ENABLE)); in meson_vpu_init()
535 priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE)); in meson_vpu_init()
537 priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE)); in meson_vpu_init()
550 priv->io_base + _REG(VIU_OSD_BLEND_CTRL)); in meson_vpu_init()
552 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_vpu_init()
554 priv->io_base + _REG(OSD2_BLEND_SRC_CTRL)); in meson_vpu_init()
555 writel(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); in meson_vpu_init()
556 writel(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); in meson_vpu_init()
557 writel(0, priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0)); in meson_vpu_init()
558 writel(0, priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA)); in meson_vpu_init()
560 priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpu_init()