Lines Matching refs:regvalue
61 u32 regvalue; in nx_disp_top_set_resconvmux() local
64 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_resconvmux()
65 writel((u32)regvalue, &pregister->resconv_mux_ctrl); in nx_disp_top_set_resconvmux()
71 u32 regvalue; in nx_disp_top_set_hdmimux() local
74 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_hdmimux()
75 writel((u32)regvalue, &pregister->interconv_mux_ctrl); in nx_disp_top_set_hdmimux()
81 u32 regvalue; in nx_disp_top_set_mipimux() local
84 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_mipimux()
85 writel((u32)regvalue, &pregister->mipi_mux_ctrl); in nx_disp_top_set_mipimux()
91 u32 regvalue; in nx_disp_top_set_lvdsmux() local
94 regvalue = (benb << 31) | (sel << 0); in nx_disp_top_set_lvdsmux()
95 writel((u32)regvalue, &pregister->lvds_mux_ctrl); in nx_disp_top_set_lvdsmux()
143 u32 regvalue; in nx_disp_top_set_hdmifield() local
146 regvalue = ((enable & 0x01) << 0) | ((init_val & 0x01) << 1) | in nx_disp_top_set_hdmifield()
149 writel(regvalue, &pregister->hdmifieldctrl); in nx_disp_top_set_hdmifield()
150 regvalue = ((field_use & 0x01) << 31) | ((muxsel & 0x01) << 30) | in nx_disp_top_set_hdmifield()
152 writel(regvalue, &pregister->greg0); in nx_disp_top_set_hdmifield()
158 u32 regvalue; in nx_disp_top_set_padclock() local
161 regvalue = readl(&pregister->greg1); in nx_disp_top_set_padclock()
163 regvalue = regvalue & (~(0x7 << 3)); in nx_disp_top_set_padclock()
164 regvalue = regvalue | (padclk_cfg << 3); in nx_disp_top_set_padclock()
166 regvalue = regvalue & (~(0x7 << 6)); in nx_disp_top_set_padclock()
167 regvalue = regvalue | (padclk_cfg << 6); in nx_disp_top_set_padclock()
169 regvalue = regvalue & (~(0x7 << 0)); in nx_disp_top_set_padclock()
170 regvalue = regvalue | (padclk_cfg << 0); in nx_disp_top_set_padclock()
172 writel(regvalue, &pregister->greg1); in nx_disp_top_set_padclock()
178 u32 regvalue; in nx_disp_top_set_lcdif_enb() local
181 regvalue = readl(&pregister->greg1); in nx_disp_top_set_lcdif_enb()
182 regvalue = regvalue & (~(0x1 << 9)); in nx_disp_top_set_lcdif_enb()
183 regvalue = regvalue | ((enb & 0x1) << 9); in nx_disp_top_set_lcdif_enb()
184 writel(regvalue, &pregister->greg1); in nx_disp_top_set_lcdif_enb()