Lines Matching refs:dpcctrl0
64 regvalue = pregister->dpcctrl0; in nx_dpc_set_interrupt_enable()
68 writel(regvalue, &pregister->dpcctrl0); in nx_dpc_set_interrupt_enable()
76 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & in nx_dpc_get_interrupt_enable()
91 read_value = pregister->dpcctrl0 & ~(intpend_mask | intenb_mask); in nx_dpc_set_interrupt_enable32()
94 &pregister->dpcctrl0); in nx_dpc_set_interrupt_enable32()
102 return (u32)((__g_module_variables[module_index].pregister->dpcctrl0 & in nx_dpc_get_interrupt_enable32()
111 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & in nx_dpc_get_interrupt_pending()
120 return (u32)((__g_module_variables[module_index].pregister->dpcctrl0 & in nx_dpc_get_interrupt_pending32()
131 regvalue = pregister->dpcctrl0; in nx_dpc_clear_interrupt_pending()
134 writel(regvalue, &pregister->dpcctrl0); in nx_dpc_clear_interrupt_pending()
145 read_value = pregister->dpcctrl0 & ~intpend_mask; in nx_dpc_clear_interrupt_pending32()
148 &pregister->dpcctrl0); in nx_dpc_clear_interrupt_pending32()
161 regvalue = pregister->dpcctrl0; in nx_dpc_set_interrupt_enable_all()
165 writel(regvalue, &pregister->dpcctrl0); in nx_dpc_set_interrupt_enable_all()
173 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & in nx_dpc_get_interrupt_enable_all()
182 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & in nx_dpc_get_interrupt_pending_all()
193 regvalue = pregister->dpcctrl0; in nx_dpc_clear_interrupt_pending_all()
196 writel(regvalue, &pregister->dpcctrl0); in nx_dpc_clear_interrupt_pending_all()
207 pend = ((pregister->dpcctrl0 >> intenb_pos) && in nx_dpc_get_interrupt_pending_number()
208 (pregister->dpcctrl0 >> intpend_pos)); in nx_dpc_get_interrupt_pending_number()
476 read_value = pregister->dpcctrl0; in nx_dpc_set_dpc_enable()
480 writel(read_value, &pregister->dpcctrl0); in nx_dpc_set_dpc_enable()
488 return (int)((__g_module_variables[module_index].pregister->dpcctrl0 & in nx_dpc_get_dpc_enable()
505 temp = pregister->dpcctrl0; in nx_dpc_set_delay()
509 writel(temp, &pregister->dpcctrl0); in nx_dpc_set_delay()
530 temp = __g_module_variables[module_index].pregister->dpcctrl0; in nx_dpc_get_delay()
613 temp = pregister->dpcctrl0; in nx_dpc_set_mode()
632 writel(temp, &pregister->dpcctrl0); in nx_dpc_set_mode()
691 temp = __g_module_variables[module_index].pregister->dpcctrl0; in nx_dpc_get_mode()
750 temp = pregister->dpcctrl0; in nx_dpc_set_hsync()
757 writel(temp, &pregister->dpcctrl0); in nx_dpc_set_hsync()
785 *pbinvhsync = (pregister->dpcctrl0 & polhsync) ? 1 : 0; in nx_dpc_get_hsync()
815 temp = pregister->dpcctrl0; in nx_dpc_set_vsync()
822 writel(temp, &pregister->dpcctrl0); in nx_dpc_set_vsync()
866 *pbinvvsync = (pregister->dpcctrl0 & polvsync) ? 1 : 0; in nx_dpc_get_vsync()
988 regvalue = readl(&pregister->dpcctrl0) & 0xfff0ul; in nx_dpc_set_sync()
991 writel((u32)regvalue, &pregister->dpcctrl0); in nx_dpc_set_sync()
1038 regvalue = readl(&pregister->dpcctrl0) & 0x0efful; in nx_dpc_set_enable()
1042 writel((u32)regvalue, &pregister->dpcctrl0); in nx_dpc_set_enable()
1233 regvalue = readl(&pregister->dpcctrl0) & 0x0eff; in nx_dpc_set_enable_with_interlace()
1234 regvalue = readl(&pregister->dpcctrl0) & 0x0eff; in nx_dpc_set_enable_with_interlace()
1240 writel((u16)regvalue, &pregister->dpcctrl0); in nx_dpc_set_enable_with_interlace()
1337 temp = readl(&pregister->dpcctrl0); in nx_dpc_set_encenable()
1343 writel((temp | encmode), &pregister->dpcctrl0); in nx_dpc_set_encenable()
1353 return (readl(&pregister->dpcctrl0) & encrst) ? 1 : 0; in nx_dpc_get_encenable()