Lines Matching refs:rk_mipi_dsi_write
51 static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) in rk_mipi_dsi_write() function
90 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ); in rk_mipi_dsi_enable()
91 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ); in rk_mipi_dsi_enable()
92 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ in rk_mipi_dsi_enable()
95 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ); in rk_mipi_dsi_enable()
96 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ); in rk_mipi_dsi_enable()
97 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ); in rk_mipi_dsi_enable()
98 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ); in rk_mipi_dsi_enable()
102 rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val); in rk_mipi_dsi_enable()
105 rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val); in rk_mipi_dsi_enable()
108 rk_mipi_dsi_write(regs, DATAEN_ACTIVE_LOW, val); in rk_mipi_dsi_enable()
111 rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val); in rk_mipi_dsi_enable()
114 rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE); in rk_mipi_dsi_enable()
117 rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE); in rk_mipi_dsi_enable()
120 rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0); in rk_mipi_dsi_enable()
129 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1); in rk_mipi_dsi_enable()
132 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); in rk_mipi_dsi_enable()
135 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT); in rk_mipi_dsi_enable()
138 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT); in rk_mipi_dsi_enable()
141 rk_mipi_dsi_write(regs, LP_CMD_EN, 1); in rk_mipi_dsi_enable()
142 rk_mipi_dsi_write(regs, LP_HFP_EN, 1); in rk_mipi_dsi_enable()
143 rk_mipi_dsi_write(regs, LP_VACT_EN, 1); in rk_mipi_dsi_enable()
144 rk_mipi_dsi_write(regs, LP_VFP_EN, 1); in rk_mipi_dsi_enable()
145 rk_mipi_dsi_write(regs, LP_VBP_EN, 1); in rk_mipi_dsi_enable()
146 rk_mipi_dsi_write(regs, LP_VSA_EN, 1); in rk_mipi_dsi_enable()
149 rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a); in rk_mipi_dsi_enable()
152 rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk); in rk_mipi_dsi_enable()
155 rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8); in rk_mipi_dsi_enable()
158 rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32); in rk_mipi_dsi_enable()
159 rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1); in rk_mipi_dsi_enable()
160 rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14); in rk_mipi_dsi_enable()
161 rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10); in rk_mipi_dsi_enable()
162 rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710); in rk_mipi_dsi_enable()
165 rk_mipi_dsi_write(regs, SHUTDOWNZ, 1); in rk_mipi_dsi_enable()
177 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); in rk_mipi_phy_write()
178 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code); in rk_mipi_phy_write()
179 rk_mipi_dsi_write(regs, PHY_TESTEN, 1); in rk_mipi_phy_write()
180 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); in rk_mipi_phy_write()
181 rk_mipi_dsi_write(regs, PHY_TESTEN, 0); in rk_mipi_phy_write()
185 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0); in rk_mipi_phy_write()
186 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]); in rk_mipi_phy_write()
187 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1); in rk_mipi_phy_write()
224 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0); in rk_mipi_phy_enable()
225 rk_mipi_dsi_write(regs, PHY_RSTZ, 0); in rk_mipi_phy_enable()
226 rk_mipi_dsi_write(regs, PHY_TESTCLR, 1); in rk_mipi_phy_enable()
229 rk_mipi_dsi_write(regs, PHY_TESTCLR, 0); in rk_mipi_phy_enable()
323 rk_mipi_dsi_write(regs, N_LANES, 0x03); in rk_mipi_phy_enable()
324 rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1); in rk_mipi_phy_enable()
325 rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1); in rk_mipi_phy_enable()
326 rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1); in rk_mipi_phy_enable()
327 rk_mipi_dsi_write(regs, PHY_RSTZ, 1); in rk_mipi_phy_enable()