Lines Matching refs:pll
35 u32 pll; member
98 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
105 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_init()
106 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
152 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
156 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
159 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
161 setbits_le32(&phy->pll, tmp + 2); in sunxi_dw_hdmi_phy_set()
163 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
170 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
174 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
177 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
178 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
184 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
188 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
191 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
192 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
198 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
202 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
205 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
206 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()