Lines Matching refs:dp
43 static inline u32 tegra_dpaux_readl(struct tegra_dp_priv *dp, u32 reg) in tegra_dpaux_readl() argument
45 return readl((u32 *)dp->regs + reg); in tegra_dpaux_readl()
48 static inline void tegra_dpaux_writel(struct tegra_dp_priv *dp, u32 reg, in tegra_dpaux_writel() argument
51 writel(val, (u32 *)dp->regs + reg); in tegra_dpaux_writel()
54 static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dp_priv *dp, in tegra_dc_dpaux_poll_register() argument
64 reg_val = tegra_dpaux_readl(dp, reg); in tegra_dc_dpaux_poll_register()
78 static inline int tegra_dpaux_wait_transaction(struct tegra_dp_priv *dp) in tegra_dpaux_wait_transaction() argument
82 if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, in tegra_dpaux_wait_transaction()
92 static int tegra_dc_dpaux_write_chunk(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dpaux_write_chunk() argument
116 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); in tegra_dc_dpaux_write_chunk()
119 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), temp_data); in tegra_dc_dpaux_write_chunk()
123 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); in tegra_dc_dpaux_write_chunk()
135 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); in tegra_dc_dpaux_write_chunk()
137 if (tegra_dpaux_wait_transaction(dp)) in tegra_dc_dpaux_write_chunk()
140 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dc_dpaux_write_chunk()
150 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_write_chunk()
166 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_write_chunk()
189 static int tegra_dc_dpaux_read_chunk(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dpaux_read_chunk() argument
214 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dc_dpaux_read_chunk()
220 tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); in tegra_dc_dpaux_read_chunk()
222 reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); in tegra_dc_dpaux_read_chunk()
233 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); in tegra_dc_dpaux_read_chunk()
235 if (tegra_dpaux_wait_transaction(dp)) in tegra_dc_dpaux_read_chunk()
238 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dc_dpaux_read_chunk()
248 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_read_chunk()
264 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, in tegra_dc_dpaux_read_chunk()
280 temp_data[i] = tegra_dpaux_readl(dp, in tegra_dc_dpaux_read_chunk()
298 static int tegra_dc_dpaux_read(struct tegra_dp_priv *dp, u32 cmd, u32 addr, in tegra_dc_dpaux_read() argument
310 ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, in tegra_dc_dpaux_read()
326 static int tegra_dc_dp_dpcd_read(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dp_dpcd_read() argument
333 ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, in tegra_dc_dp_dpcd_read()
343 static int tegra_dc_dp_dpcd_write(struct tegra_dp_priv *dp, u32 cmd, in tegra_dc_dp_dpcd_write() argument
350 ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, in tegra_dc_dp_dpcd_write()
360 static int tegra_dc_i2c_aux_read(struct tegra_dp_priv *dp, u32 i2c_addr, in tegra_dc_i2c_aux_read() argument
371 dp, DPAUX_DP_AUXCTL_CMD_MOTWR, i2c_addr, in tegra_dc_i2c_aux_read()
380 dp, DPAUX_DP_AUXCTL_CMD_I2CRD, i2c_addr, in tegra_dc_i2c_aux_read()
396 static void tegra_dc_dpaux_enable(struct tegra_dp_priv *dp) in tegra_dc_dpaux_enable() argument
399 tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff); in tegra_dc_dpaux_enable()
401 tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0); in tegra_dc_dpaux_enable()
403 tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, in tegra_dc_dpaux_enable()
409 tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, in tegra_dc_dpaux_enable()
414 static void tegra_dc_dp_dump_link_cfg(struct tegra_dp_priv *dp, in tegra_dc_dp_dump_link_cfg() argument
451 static int _tegra_dp_lower_link_config(struct tegra_dp_priv *dp, in _tegra_dp_lower_link_config() argument
483 static int tegra_dc_dp_calc_config(struct tegra_dp_priv *dp, in tegra_dc_dp_calc_config() argument
647 tegra_dc_dp_dump_link_cfg(dp, link_cfg); in tegra_dc_dp_calc_config()
655 struct tegra_dp_priv *dp, in tegra_dc_dp_init_max_link_cfg() argument
664 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LANE_COUNT, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
675 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_DOWNSPREAD, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
681 ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_AUX_RD_INTERVAL, in tegra_dc_dp_init_max_link_cfg()
685 ret = tegra_dc_dp_dpcd_read(dp, DP_MAX_LINK_RATE, in tegra_dc_dp_init_max_link_cfg()
698 ret = tegra_dc_dp_dpcd_read(dp, DP_EDP_CONFIGURATION_CAP, &dpcd_data); in tegra_dc_dp_init_max_link_cfg()
714 tegra_dc_dp_calc_config(dp, timing, link_cfg); in tegra_dc_dp_init_max_link_cfg()
737 static int tegra_dp_set_link_bandwidth(struct tegra_dp_priv *dp, in tegra_dp_set_link_bandwidth() argument
744 return tegra_dc_dp_dpcd_write(dp, DP_LINK_BW_SET, link_bw); in tegra_dp_set_link_bandwidth()
747 static int tegra_dp_set_lane_count(struct tegra_dp_priv *dp, in tegra_dp_set_lane_count() argument
758 ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data); in tegra_dp_set_lane_count()
768 static int tegra_dc_dp_link_trained(struct tegra_dp_priv *dp, in tegra_dc_dp_link_trained() argument
777 ret = tegra_dc_dp_dpcd_read(dp, (lane / 2) ? in tegra_dc_dp_link_trained()
795 static int tegra_dp_channel_eq_status(struct tegra_dp_priv *dp, in tegra_dp_channel_eq_status() argument
805 ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data); in tegra_dp_channel_eq_status()
827 ret = tegra_dc_dp_dpcd_read(dp, in tegra_dp_channel_eq_status()
839 static int tegra_dp_clock_recovery_status(struct tegra_dp_priv *dp, in tegra_dp_clock_recovery_status() argument
848 ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt), in tegra_dp_clock_recovery_status()
864 static int tegra_dp_lt_adjust(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_lt_adjust() argument
874 ret = tegra_dc_dp_dpcd_read(dp, DP_ADJUST_REQUEST_LANE0_1 + cnt, in tegra_dp_lt_adjust()
890 ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2, in tegra_dp_lt_adjust()
904 static void tegra_dp_wait_aux_training(struct tegra_dp_priv *dp, in tegra_dp_wait_aux_training() argument
914 static void tegra_dp_tpg(struct tegra_dp_priv *dp, u32 tp, u32 n_lanes, in tegra_dp_tpg() argument
921 tegra_dc_sor_set_dp_linkctl(dp->sor, 1, tp, cfg); in tegra_dp_tpg()
922 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, data); in tegra_dp_tpg()
925 static int tegra_dp_link_config(struct tegra_dp_priv *dp, in tegra_dp_link_config() argument
938 ret = tegra_dc_dp_dpcd_read(dp, DP_SET_POWER, &dpcd_data); in tegra_dp_link_config()
947 ret = tegra_dc_dp_dpcd_write(dp, DP_SET_POWER, in tegra_dp_link_config()
960 ret = tegra_dc_dp_set_assr(dp, dp->sor, 1); in tegra_dp_link_config()
965 ret = tegra_dp_set_link_bandwidth(dp, dp->sor, link_cfg->link_bw); in tegra_dp_link_config()
970 ret = tegra_dp_set_lane_count(dp, link_cfg, dp->sor); in tegra_dp_link_config()
975 tegra_dc_sor_set_dp_linkctl(dp->sor, 1, training_pattern_none, in tegra_dp_link_config()
981 static int tegra_dp_lower_link_config(struct tegra_dp_priv *dp, in tegra_dp_lower_link_config() argument
991 ret = _tegra_dp_lower_link_config(dp, cfg); in tegra_dp_lower_link_config()
993 ret = tegra_dc_dp_calc_config(dp, timing, cfg); in tegra_dp_lower_link_config()
995 ret = tegra_dp_link_config(dp, cfg); in tegra_dp_lower_link_config()
1003 tegra_dp_link_config(dp, &tmp_cfg); in tegra_dp_lower_link_config()
1007 static int tegra_dp_lt_config(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_lt_config() argument
1010 struct udevice *sor = dp->sor; in tegra_dp_lt_config()
1052 tegra_dp_disable_tx_pu(dp->sor); in tegra_dp_lt_config()
1067 tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val); in tegra_dp_lt_config()
1083 tegra_dc_dp_dpcd_write(dp, in tegra_dp_lt_config()
1092 static int _tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], in _tegra_dp_channel_eq() argument
1103 ret = tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, in _tegra_dp_channel_eq()
1107 tegra_dp_lt_config(dp, pe, vs, pc, cfg); in _tegra_dp_channel_eq()
1110 tegra_dp_wait_aux_training(dp, false, cfg); in _tegra_dp_channel_eq()
1112 if (!tegra_dp_clock_recovery_status(dp, cfg)) { in _tegra_dp_channel_eq()
1117 if (!tegra_dp_channel_eq_status(dp, cfg)) in _tegra_dp_channel_eq()
1124 static int tegra_dp_channel_eq(struct tegra_dp_priv *dp, u32 pe[4], u32 vs[4], in tegra_dp_channel_eq() argument
1136 tegra_dp_tpg(dp, tp_src, n_lanes, cfg); in tegra_dp_channel_eq()
1138 ret = _tegra_dp_channel_eq(dp, pe, vs, pc, pc_supported, n_lanes, cfg); in tegra_dp_channel_eq()
1140 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg); in tegra_dp_channel_eq()
1145 static int _tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], in _tegra_dp_clk_recovery() argument
1154 tegra_dp_lt_config(dp, pe, vs, pc, cfg); in _tegra_dp_clk_recovery()
1155 tegra_dp_wait_aux_training(dp, true, cfg); in _tegra_dp_clk_recovery()
1157 if (tegra_dp_clock_recovery_status(dp, cfg)) in _tegra_dp_clk_recovery()
1161 tegra_dp_lt_adjust(dp, pe, vs, pc, pc_supported, cfg); in _tegra_dp_clk_recovery()
1172 static int tegra_dp_clk_recovery(struct tegra_dp_priv *dp, u32 pe[4], in tegra_dp_clk_recovery() argument
1180 tegra_dp_tpg(dp, training_pattern_1, n_lanes, cfg); in tegra_dp_clk_recovery()
1182 err = _tegra_dp_clk_recovery(dp, pe, vs, pc, pc_supported, n_lanes, in tegra_dp_clk_recovery()
1185 tegra_dp_tpg(dp, training_pattern_disabled, n_lanes, cfg); in tegra_dp_clk_recovery()
1190 static int tegra_dc_dp_full_link_training(struct tegra_dp_priv *dp, in tegra_dc_dp_full_link_training() argument
1194 struct udevice *sor = dp->sor; in tegra_dc_dp_full_link_training()
1205 err = tegra_dp_clk_recovery(dp, pe, vs, pc, cfg); in tegra_dc_dp_full_link_training()
1207 if (!tegra_dp_lower_link_config(dp, timing, cfg)) in tegra_dc_dp_full_link_training()
1214 err = tegra_dp_channel_eq(dp, pe, vs, pc, cfg); in tegra_dc_dp_full_link_training()
1216 if (!tegra_dp_lower_link_config(dp, timing, cfg)) in tegra_dc_dp_full_link_training()
1223 tegra_dc_dp_dump_link_cfg(dp, cfg); in tegra_dc_dp_full_link_training()
1235 static int tegra_dc_dp_fast_link_training(struct tegra_dp_priv *dp, in tegra_dc_dp_fast_link_training() argument
1249 tegra_dc_dp_dpcd_write(dp, DP_MAIN_LINK_CHANNEL_CODING_SET, in tegra_dc_dp_fast_link_training()
1254 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, in tegra_dc_dp_fast_link_training()
1258 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); in tegra_dc_dp_fast_link_training()
1262 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, in tegra_dc_dp_fast_link_training()
1272 tegra_dc_dp_set_assr(dp, sor, link_cfg->scramble_ena); in tegra_dc_dp_fast_link_training()
1275 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, in tegra_dc_dp_fast_link_training()
1278 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24); in tegra_dc_dp_fast_link_training()
1282 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, DP_LANE0_1_STATUS, in tegra_dc_dp_fast_link_training()
1291 tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, 0); in tegra_dc_dp_fast_link_training()
1293 if (tegra_dc_dp_link_trained(dp, link_cfg)) { in tegra_dc_dp_fast_link_training()
1306 static int tegra_dp_do_link_training(struct tegra_dp_priv *dp, in tegra_dp_do_link_training() argument
1316 ret = tegra_dc_dp_fast_link_training(dp, link_cfg, sor); in tegra_dp_do_link_training()
1324 ret = tegra_dc_sor_set_voltage_swing(dp->sor, link_cfg); in tegra_dp_do_link_training()
1333 ret = tegra_dc_dp_full_link_training(dp, timing, link_cfg); in tegra_dp_do_link_training()
1350 static int tegra_dc_dp_explore_link_cfg(struct tegra_dp_priv *dp, in tegra_dc_dp_explore_link_cfg() argument
1377 if ((!tegra_dc_dp_calc_config(dp, timing, &temp_cfg)) && in tegra_dc_dp_explore_link_cfg()
1378 (!tegra_dp_link_config(dp, &temp_cfg)) && in tegra_dc_dp_explore_link_cfg()
1379 (!tegra_dp_do_link_training(dp, &temp_cfg, timing, sor))) in tegra_dc_dp_explore_link_cfg()
1386 static int tegra_dp_hpd_plug(struct tegra_dp_priv *dp) in tegra_dp_hpd_plug() argument
1394 val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); in tegra_dp_hpd_plug()
1403 static int tegra_dc_dp_sink_out_of_sync(struct tegra_dp_priv *dp, u32 delay_ms) in tegra_dc_dp_sink_out_of_sync() argument
1411 ret = tegra_dc_dp_dpcd_read(dp, DP_SINK_STATUS, &dpcd_data); in tegra_dc_dp_sink_out_of_sync()
1424 static int tegra_dc_dp_check_sink(struct tegra_dp_priv *dp, in tegra_dc_dp_check_sink() argument
1443 if (!tegra_dc_dp_sink_out_of_sync(dp, link_cfg->frame_in_ms * in tegra_dc_dp_check_sink()
1452 ret = tegra_dc_sor_detach(dp->dc_dev, dp->sor); in tegra_dc_dp_check_sink()
1455 if (tegra_dc_dp_explore_link_cfg(dp, link_cfg, dp->sor, in tegra_dc_dp_check_sink()
1461 tegra_dc_sor_set_power_state(dp->sor, 1); in tegra_dc_dp_check_sink()
1462 tegra_dc_sor_attach(dp->dc_dev, dp->sor, link_cfg, timing); in tegra_dc_dp_check_sink()