Lines Matching refs:portnum
46 u8 portnum; /* 0 or 1 */ member
75 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dp_disable_tx_pu()
84 tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg); in tegra_dp_set_pe_vs_pc()
85 tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg); in tegra_dp_set_pe_vs_pc()
87 tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask, in tegra_dp_set_pe_vs_pc()
149 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_dp_linkctl()
162 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); in tegra_dc_sor_set_dp_linkctl()
220 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_dplanes()
238 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_power_dplanes()
250 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_set_panel_power()
257 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_set_panel_power()
285 reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum)); in tegra_dc_sor_set_dp_mode()
301 tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val); in tegra_dc_sor_set_dp_mode()
378 reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum)); in tegra_dc_sor_set_internal_panel()
386 tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val); in tegra_dc_sor_set_internal_panel()
399 DP_LINKCTL(sor->portnum)); in tegra_dc_sor_read_link_config()
433 reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum)); in tegra_dc_sor_set_lane_count()
452 tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val); in tegra_dc_sor_set_lane_count()
479 reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_up()
499 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_power_up()
838 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), in tegra_dc_sor_set_lane_parm()
840 tegra_sor_writel(sor, PR(sor->portnum), in tegra_dc_sor_set_lane_parm()
842 tegra_sor_writel(sor, POSTCURSOR(sor->portnum), in tegra_dc_sor_set_lane_parm()
849 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_set_lane_parm()
856 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); in tegra_dc_sor_set_lane_parm()
859 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); in tegra_dc_sor_set_lane_parm()
883 tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current); in tegra_dc_sor_set_voltage_swing()
884 tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis); in tegra_dc_sor_set_voltage_swing()
921 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); in tegra_dc_sor_power_down_unused_lanes()
952 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()
956 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()