Lines Matching defs:Nb
73 #define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ argument
90 #define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ argument
136 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
138 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ argument
139 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ argument
141 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ argument
410 #define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ argument
412 #define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ argument
414 #define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ argument
416 #define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ argument
418 #define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ argument
420 #define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ argument
422 #define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ argument
424 #define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ argument
1114 #define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ argument
1142 #define OSSR_M(Nb) /* Match detected [0..3] */ \ argument
1152 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ argument
1276 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ argument
1533 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ argument
1564 #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ argument
1648 #define IC_GPIO(Nb) /* GPIO [0..10] */ \ argument
1670 #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ argument
1678 #define IC_OST(Nb) /* OS Timer match [0..3] */ \ argument
1735 #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ argument
1816 #define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ argument
1839 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ argument
1909 #define _MSC(Nb) /* Static memory Control reg. */ \ argument
1933 #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ argument
2009 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
2148 #define _DDAR(Nb) /* DMA Device Address Reg. */ \ argument
2151 #define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ argument
2154 #define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ argument
2157 #define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ argument
2160 #define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ argument
2163 #define _DBTA(Nb) /* DMA Buffer Transfer count */ \ argument
2166 #define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ argument
2169 #define _DBTB(Nb) /* DMA Buffer Transfer count */ \ argument