Lines Matching refs:n
75 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ argument
76 (LOG2(n) - IFC_AMASK_SHIFT))
117 #define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT) argument
141 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) argument
170 #define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) argument
178 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) argument
182 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) argument
201 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) argument
203 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) argument
205 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) argument
207 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) argument
213 #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) argument
215 #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) argument
217 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) argument
219 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) argument
225 #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) argument
227 #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) argument
229 #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) argument
235 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) argument
242 #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) argument
244 #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) argument
246 #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) argument
248 #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) argument
254 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) argument
256 #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) argument
258 #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) argument
264 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) argument
266 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) argument
268 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) argument
270 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) argument
277 #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) argument
279 #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) argument
281 #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) argument
283 #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) argument
289 #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) argument
291 #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) argument
297 #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) argument
299 #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) argument
301 #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) argument
355 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) argument
359 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) argument
388 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) argument
554 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) argument
556 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) argument
558 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) argument
650 #define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) argument
729 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) argument
733 #define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) argument