Lines Matching defs:stm32_rcc_regs
59 struct stm32_rcc_regs { struct
60 u32 cr; /* RCC clock control */
61 u32 pllcfgr; /* RCC PLL configuration */
62 u32 cfgr; /* RCC clock configuration */
63 u32 cir; /* RCC clock interrupt */
64 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
65 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
66 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
67 u32 rsv0;
68 u32 apb1rstr; /* RCC APB1 peripheral reset */
69 u32 apb2rstr; /* RCC APB2 peripheral reset */
70 u32 rsv1[2];
71 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
72 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
73 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
74 u32 rsv2;
75 u32 apb1enr; /* RCC APB1 peripheral clock enable */
76 u32 apb2enr; /* RCC APB2 peripheral clock enable */
77 u32 rsv3[2];
78 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
79 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
80 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
81 u32 rsv4;
82 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
83 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
84 u32 rsv5[2];
85 u32 bdcr; /* RCC Backup domain control */
86 u32 csr; /* RCC clock control & status */
87 u32 rsv6[2];
88 u32 sscgr; /* RCC spread spectrum clock generation */
89 u32 plli2scfgr; /* RCC PLLI2S configuration */
91 u32 pllsaicfgr; /* PLLSAI configuration */
92 u32 dckcfgr; /* dedicated clocks configuration register */
94 u32 dckcfgr2; /* dedicated clocks configuration register */