ELF@@WXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~{@@{|D_@{ @@{_{@ *@/7 @{¨_{@0@a6@?6{_{S@rT@SA{¨_{S**!04svSc a|S$c( R@, R8!`R0BSA{èpl011: device parameters ignored (%s)pl011: unexpected register size: %zx{S@*`@9 4#RBRR*7@@`T#R"RR @RRRSA@{Ĩ_pl011arm,pl011pl011_dev_init intNNZ:!-[Nag pah vai  ops_ Z  {     Z u u 4e  u  u 4 u  ' ) u 4 u 4  M   <u = >M- A  4 ( a b cz d  e f u Z U # upN`%p   (0upd(. PP@% 4/ufdtAJ4pd( p  Bx . _P QR2S1T US PQRpSx P QR1S1T ! "TPR0S0aNu$Tpd("P1QH#pd$(0@  { $ >% % & % % $ % % $ % % ' /% % $ o% % $ % % PQ 5 PP#u 4. u,uchu64w '] w %n ()z * ) "PP@Q $ z % & ~% % l 4D< l.un '] n %n ()z * ) "PpQ $ r ' % "< Pe (5 e4ug '] g %n ()z * ) "PP@Q & i % U ,] U-uW '] W %n ()z * ) "PP@Q $ ` - % & a % +M ,M1u-pdO(./P.+0 ,0*0! ,!'1val!62 2 $2 2[ 2 2t % UB$ > $ > : ; 9 I&I I& : ; 9  : ; 9 I8 : ; 9 I8 ' I 'I'I> I: ; 9 ( 4: ; 9 I4: ; 9 I?I!I/ .: ; 9 '@B: ; 9 IB4: ; 9 IB 4: ; 9 IBB1B.: ; 9 'I@B: ; 9 IB4I4 U 1!1"1#.?: ; 9 '@B$1RB X Y W %1B&1RB X Y W '1RB UX Y W ( U)41B* 1+.: ; 9 'I ,: ; 9 I-4: ; 9 I. /4: ; 9 I0.: ; 9 ' 1: ; 9 I2.?<n: ; 9 PpPppPP@PpPPPQdQReRSUScP@PQPPPPdppPQpQRcRSeSPS --Qp$Sp(0p0p0`p,Pp8 p0PpPQcpPPpPppPP@PpPpcPPcPPdPcppPpP@PcPdPpPPPpPppPP@PpPpPpPPPpPppPP@PpPp0p($4,D                             !"  #$% & '  ( i) * +, - . /01 23 4     56 7 "#$%&'()*+,-./23456789:;>?@ABCDEFGHJK    !$&'()*+,-./123456789:;<=>?@ABCDEFGHIJKLMNOPQRSXYZ[\^bdfgijklmnpqrstuvwyz{|}~ "$&'()*5789?@BCEFGIMQTW "'/0146iloru!"#4'(*"'/6=DIOQT_fmt{   !&,/12);hijkmnoprstuyz{|~ !"$%&'(*+,-.01234"#$Y^az{|S+I !"#    !"#$%&'()*+,-./03456789<=>?@ABEFGHKLMPQRUXZ[\]^_`abcdefghijklmnopqrstuxyz{|}~   (),14DLRU`bcijlmou}~ !"$%'-246;B  !#opqrstu"#$%&'()+,./02678;>?@ABCDEFGHIKLMNOPQRSUVWXYZ[\]^ab  !"%&'()*,-./12346789;<>?ABCDFGHIKLMPV^_`abcdefghijklprtvy{}*  2  "$%&'./0124678@BDEFGMRY[]lmt !"#$%&'(+,-./01234EUX`knz #$&+,#(+4<EMUcqz~ FGHJLM$%()*-./67FY\]%&),/2     !"i  core/driverscore/include/home/test/workspace/code/optee_3.16/toolchains/aarch64/lib/gcc/aarch64-none-linux-gnu/10.2.1/includelib/libutils/isoc/includelib/libutils/ext/includelib/libutee/includecore/include/mmcore/include/driverscore/include/kernel./out/arm/include/generatedcore/arch/arm/include/mmlib/libutils/isoc/include/syscore/arch/arm/include/kernelcore/arch/arm/includecore/arch/arm/plat-vexpress/.core/include/dt-bindings/interrupt-controllerpl011.cio.hstddef.hstdint.htypes_ext.htee_api_types.hcore_memprot.hserial.hpl011.hdt.h malloc.htrace.hconf.h assert.hcompiler.hstdarg.hstdbool.htrace_levels.hlimits.hinttypes.hunistd.hcore_mmu.h user_ta.h tee_ta_manager.h mutex.h refcount.h atomic.hwait_queue.h queue.h tee_common.h stdlib.hts_manager.h tee_api_defines.htee_mmu_types.hutil.huser_ta_header.hutee_types.huser_mode_ctx_struct.h thread.h arm.harm64.hcdefs.h vfp.h pgt_cache.h file.hutee_defines.htee_api_defines_extensions.htee_mm.hscattered_array.hkeep.hplatform_config.hgeneric_ram_layout.h interrupt.h irq.hpanic.h  f l . l G  8 !   !-!"" ! V$ \ $. \ (  $   v  $  P  .P   6.#  e  .`    .0    f#! 0 1  !  "     ~ ~.~.!   K z &   /X "X#  / 5 /<0 ! TEE_INT_CORE_API_SPEC_VERSION 0x0000000ACTR_CWG_SHIFT U(24)TEE_ALG_HKDF_SHA256_DERIVE_KEY 0x800040C0SLIST_REMOVE(head,elm,type,field) do { if ((head)->slh_first == (elm)) { SLIST_REMOVE_HEAD((head), field); } else { struct type *curelm = (head)->slh_first; while(curelm->field.sle_next != (elm)) curelm = curelm->field.sle_next; curelm->field.sle_next = curelm->field.sle_next->field.sle_next; } } while ( 0)TEE_PANIC_ID_TEE_GETOPERATIONINFOMULTIPLE 0x00000C08__FLT64X_HAS_QUIET_NAN__ 1TA_FLAG_DEVICE_ENUM (1 << 9)__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__unsigned int__UINT16_MAX__ 0xffffQUEUEDEBUG_CIRCLEQ_ELM(head,elm,field) SIMPLEQ_FOREACH(var,head,field) for ((var) = ((head)->sqh_first); (var); (var) = ((var)->field.sqe_next))TEE_TYPE_DES 0xA0000011DEFINE_U32_REG_WRITE_FUNC(reg) DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg)TA_FLAG_INSTANCE_KEEP_ALIVE (1 << 4)TEE_API_DEFINES_H __ARM_FEATURE_MATMUL_INT8TEE_TYPE_SM2_DSA_PUBLIC_KEY 0xA0000045TAILQ_HEAD(name,type) _TAILQ_HEAD(name, struct type,)PL011_REG_SIZE 0x1000UART_LCRH_EPS (1 << 2)__FLT32_DIG__ 6_WCHAR_T_DEFINED SPSR_32(mode,isa,aif) (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT)barrier() asm volatile ("" : : : "memory")CFG_TA_MBEDTLS_SELF_TEST 1SHRT_MAX __SHRT_MAX____func____ARM_ALIGN_MAX_PWR 28nex_calloc(nmemb,size) calloc(nmemb, size)UART_LCRH_WLEN_7 (2 << 5)CFG_ZLIB 1CFG_TEE_IMPL_DESCR OPTEECFG_CRYPTO_CBC 1__SIZEOF_SHORT__ 2__FLT64_MANT_DIG__ 53QUEUEDEBUG_LIST_OP(elm,field) PRId64 __PRI64_PREFIX "d"SLIST_INIT(head) do { (head)->slh_first = NULL; } while ( 0)__FLT_MAX_10_EXP__ 38dev_allocSLIST_FOREACH(var,head,field) for((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next)TEE_ERROR_COMMUNICATION 0xFFFF000EMIN(a,b) (__extension__({ __typeof__(a) _a = (a); __typeof__(b) _b = (b); _a < _b ? _a : _b; }))__FLT_EVAL_METHOD_C99__ 0SCATTERED_ARRAY_DEFINE_PG_ITEM_ORDERED(array_name,order,element_type) __SCT_ARRAY_DEF_PG_ITEM1(array_name, order, __COUNTER__, element_type)TEE_TYPE_SM2_KEP_PUBLIC_KEY 0xA0000046PAR_PA_MASK (BIT64(36) - 1)TEE_BigIntSizeInU32(n) ((((n)+31)/32)+2)__UINT_LEAST32_TYPE__ unsigned intCFG_CRYPTO_SM2_KEP 1TEE_MATTR_URW (TEE_MATTR_UR | TEE_MATTR_UW)__ARM_FP_FASTTEE_ATTR_PBKDF2_PASSWORD 0xC00001C2UINT32_C(v) U(v)BIT32(nr) (UINT32_C(1) << (nr))__FLT64_MIN_10_EXP__ (-307)UINT_LEAST16_MAX UINT16_MAXCFG_CRYPTO_ECB 1CFG_PREALLOC_RPC_CACHE 1_CFG_CORE_LTC_SHA256_DESC 1__PTRDIFF_MAX__ 0x7fffffffffffffffLPRIo32 "o"UART_CR_OUT2 (1 << 13)CTR_CWG_MASK U(0xf)SPSR_64_DAIF_MASK U(0xf)CFG_CORE_BIGNUM_MAX_BITS 4096_CFG_CORE_LTC_SHA512_DESC 1TAILQ_INIT(head) do { (head)->tqh_first = NULL; (head)->tqh_last = &(head)->tqh_first; } while ( 0)_BoolUART_CR_LPE (1 << 7)TEE_PANIC_ID_TEE_ALLOCATEOPERATION 0x00000C01SCATTERED_ARRAY_DEFINE_ITEM_ORDERED(array_name,order,element_type) __SCT_ARRAY_DEF_ITEM1(array_name, order, __COUNTER__, element_type)TCR_ORGN0_SHIFT U(10)__UINT_FAST16_MAX__ 0xffffffffffffffffULTEE_ATTR_CONCAT_KDF_Z 0xC00001C1__ARM_FEATURE_SVE2_SM4TEE_ECC_CURVE_NIST_P256 0x00000003LLONG_MAX __LONG_LONG_MAX__UART_ILPR 0x20__ARM_FEATURE_PAC_DEFAULTCORTEX_A57_PART_NUM U(0xD07)CFG_CORE_CLUSTER_SHIFT 2__DBL_MAX_10_EXP__ 308CONSOLE_UART_CLK_IN_HZ 1TEE_ATTR_DSA_BASE 0xD0001231_CFG_CORE_LTC_SHA1 1__ARM_FEATURE_IDIV 1_ILP32TEE_MAIN_ALGO_CONCAT_KDF 0xC1__WCHAR_TYPE__ unsigned int__SECTION_FLAGS_RODATA ",\"a\",%progbits //"TEE_MAIN_ALGO_MD5 0x01__ELF__ 1__SIZEOF_LONG__ 8TEE_ALG_DES3_ECB_NOPAD 0x10000013__ARM_ARCH 8CFG_FTRACE_US_MS 10000tee_mtime_perftest() do { } while (0)VM_FLAG_READONLY BIT(4)UART_FR_CTS (1 << 0)SIZE_4K UINTPTR_C(0x1000)SIMPLEQ_NEXT(elm,field) ((elm)->field.sqe_next)TEE_PANIC_ID_TEE_UNMASKCANCELLATION 0x00000503__WCHAR_T__ TEE_PANIC_ID_TEE_BIGINTCONVERTTOFMM 0x00001C03uart_clkTEE_MAIN_ALGO_SM2_PKE 0x47TEE_ALLOCATOR_DESC_LENGTH 32INTTYPES_H __need___va_listIS_ALIGNED_WITH_TYPE(x,type) (__extension__({ type __is_aligned_y; IS_ALIGNED((uintptr_t)(x), __alignof__(__is_aligned_y)); }))__FLT_MAX__ 3.40282346638528859811704183484516925e+38FSLIST_REMOVE_AFTER(slistelm,field) do { (slistelm)->field.sle_next = SLIST_NEXT(SLIST_NEXT((slistelm), field), field); } while ( 0)_STDBOOL_H SCHAR_MAX __SCHAR_MAX__PGT_CACHE_SIZE ROUNDUP(CFG_NUM_THREADS * 2, PGT_NUM_PGT_PER_PAGE)TEE_ATTR_SM2_KEP_USER 0xF0000646INTMAX_MAX INT64_MAXUINT_MAX (INT_MAX * 2U + 1U)ESR_EC_WFI U(0x01)INT_LEAST32_MIN INT32_MINTEE_ALG_DES3_CBC_MAC_NOPAD 0x30000113DAIF_I BIT32(7)TEE_U32_BSWAP(x) __compiler_bswap32((x))INT_FAST64_MIN INT64_MIN_CFG_CORE_LTC_MAC 1UINT_LEAST64_MAX UINT64_MAX__FLT_HAS_INFINITY__ 1TEE_PANIC_ID_TEE_DIGESTUPDATE 0x00000D02__FLT16_MAX__ 6.55040000000000000000000000000000000e+4F16__FLT128_MIN_10_EXP__ (-4931)ARM32_CPSR_A BIT(8)TEE_ERROR_DEFER_DRIVER_INIT 0x80000000STAILQ_INSERT_AFTER(head,listelm,elm,field) do { if (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL) (head)->stqh_last = &(elm)->field.stqe_next; (listelm)->field.stqe_next = (elm); } while ( 0)linux 1TEE_PANIC_ID_TEE_INVOKETACOMMAND 0x00000402__LDBL_HAS_DENORM__ 1TEE_PANIC_ID_TEE_FREEOPERATION 0x00000C03INT_MIN (-INT_MAX - 1)ITRF_SHARED BIT(1)TEE_PANIC_ID_TEE_GETCANCELLATIONFLAG 0x00000501LIST_FOREACH(var,head,field) for ((var) = ((head)->lh_first); (var); (var) = ((var)->field.le_next))__FLT16_EPSILON__ 9.76562500000000000000000000000000000e-4F16CFG_RESERVED_VASPACE_SIZE (1024 * 1024 * 10)KERNEL_WAIT_QUEUE_H __ARM_FEATURE_SVE2TEE_MM_POOL_NO_FLAGS 0UINTMAX_MAX UINT64_MAXTEE_PANIC_ID_TEE_RESETOPERATION 0x00000C05callocPRIX64 __PRI64_PREFIX "X"KERNEL_THREAD_H base_T_PTRDIFF_ __LDBL_DIG__ 33TO_STR(x) _TO_STR(x)TEE_PANIC_ID_TEE_GENERATEKEY 0x00000804ARM32_CPSR_F_SHIFT U(6)CFG_LPAE_ADDR_SPACE_BITS 32CFG_TA_BIGNUM_MAX_BITS 2048TEE_PANIC_ID_TEE_SETOPERATIONKEY 0x00000C06INT_FAST32_MAX INT32_MAXMPIDR_MT_MASK BIT(MPIDR_MT_SHIFT)ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))CFG_ARM64_ta_arm64 1STAILQ_INIT(head) do { (head)->stqh_first = NULL; (head)->stqh_last = &(head)->stqh_first; } while ( 0)_CFG_CORE_LTC_SM2_PKE 1__INT_LEAST16_WIDTH__ 16CFG_MSG_LONG_PREFIX_MASK 0x1aSMALL_PAGE_SIZE BIT(SMALL_PAGE_SHIFT)CPACR_EL1_FPEN_EL0EL1 U(0x3)_CFG_CORE_LTC_AUTHENC 1__DBL_HAS_INFINITY__ 1__UINT_FAST64_MAX__ 0xffffffffffffffffUL__FLT16_HAS_DENORM__ 1TEE_ERROR_CIPHERTEXT_INVALID 0xF0100006CFG_AES_GCM_TABLE_BASED 1__ARM_FEATURE_ATOMICS_VA_LIST_DEFINED TEE_ATTR_DH_PRIVATE_VALUE 0xC0000232TEE_PANIC_ID_TEE_GETNEXTPROPERTY 0x00000203__SHRT_MAX__ 0x7fffCFG_ARM64_core 1TEE_ALG_DES_ECB_NOPAD 0x10000011_CFG_CORE_LTC_AES_DESC 1CFG_ARM32_ta_arm32 1__INTPTR_TYPE__ long int__wchar_t__ __FLT32_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F32_CFG_CORE_LTC_ECC 1CTR_L1IP_SHIFT U(14)__FLT32_HAS_INFINITY__ 1SPSR_32_E_SHIFT U(9)ARM32_CPSR_MODE_IRQ U(0x12)TEE_ERROR_GENERIC 0xFFFF0000INT32_MAX 0x7ffffffftrace_printfESR_EC_AARCH32_CP14_MR U(0x05)__INT_LEAST64_TYPE__ long int__INT32_MAX__ 0x7fffffff__FLT128_MIN__ 3.36210314311209350626267781732175260e-4932F128TEE_PANIC_ID_TEE_COPYOPERATION 0x00000C02TEE_USAGE_SIGN 0x00000010__GNUC_PATCHLEVEL__ 1__SIZE_MAX__ 0xffffffffffffffffUL__ARM_FEATURE_SVE_MATMUL_INT8ARM32_CPSR_MODE_MASK U(0x1f)TEE_AES_MAX_KEY_SIZE 32UL__GCC_ATOMIC_CHAR_LOCK_FREE 2TEE_ALG_MD5SHA1 0x5000000F__FLT128_MANT_DIG__ 113CFG_KERN_LINKER_ARCH aarch64SPSR_MODE_RW_SHIFT U(4)_CFG_CORE_LTC_DH 1__UINT_FAST32_TYPE__ long unsigned intTEE_ALG_MD5 0x50000001__AARCH64EL__ 1__SIZEOF_INT__ 4CFG_WARN_INSECURE 1ESR_EC_WATCHPT_EL0 U(0x34)CORE_MMU_PGDIR_LEVEL U(3)__FLT32X_MAX_10_EXP__ 308TEE_ATTR_ECC_PUBLIC_VALUE_Y 0xD0000241CFG_TZDRAM_SIZE 0x00f00000TA_PROP_STR_STACK_SIZE "gpd.ta.stackSize"TEE_ERROR_STORAGE_NO_SPACE 0xFFFF3041IRQ_TYPE_EDGE_RISING 1__SIG_ATOMIC_TYPE__ int_BSD_SIZE_T_DEFINED_ __BIGGEST_ALIGNMENT__ 16__FLT16_NORM_MAX__ 6.55040000000000000000000000000000000e+4F16TEE_PANIC_ID_TEE_GETPROPERTYNAME 0x0000020A__INT_FAST16_WIDTH__ 64TEE_ATTR_RSA_PUBLIC_EXPONENT 0xD0000230TTBR_ASID_MASK U(0xff)DT_INFO_INVALID_INTERRUPT -1TEE_DIGEST_HASH_TO_ALGO(algo) TEE_ALG_HASH_ALGO(TEE_ALG_GET_DIGEST_HASH(algo))__ARM_FEATURE_SVE2_SHA3CFG_TA_STRICT_ANNOTATION_CHECKS 1nex_memalign(alignment,size) memalign(alignment, size)__PRAGMA_REDEFINE_EXTNAME 1_CFG_CORE_LTC_CTR 1__pic__ 1CFG_CRYPTO_SM2_DSA 1DMSG_RAW(...) trace_printf_helper_raw(TRACE_DEBUG, true, __VA_ARGS__)__PIE__ 1TEE_ALG_SM2_KEP 0x60000045_CFG_CORE_LTC_VFP 1TEE_PARAM_TYPES(t0,t1,t2,t3) ((t0) | ((t1) << 4) | ((t2) << 8) | ((t3) << 12))___int_wchar_t_h __HAVE_SPECULATION_SAFE_VALUE 1DT_STATUS_OK_NSEC BIT(0)ARM32_CPSR_F BIT(6)PRIdPTR __PRIPTR_PREFIX "d"ESR_EC_WATCHPT_EL1 U(0x35)UL(v) v ## ULCFG_CRYPTO_ECC 1flushDHEXDUMP(buf,len) dhex_dump(__func__, __LINE__, TRACE_DEBUG, buf, len)TEE_TIMEOUT_INFINITE 0xFFFFFFFFARM32_CPSR_E BIT(9)__DBL_EPSILON__ ((double)2.22044604925031308084726333618164062e-16L)SLIST_INSERT_HEAD(head,elm,field) do { (elm)->field.sle_next = (head)->slh_first; (head)->slh_first = (elm); } while ( 0)TEE_OPERATION_ASYMMETRIC_CIPHER 6TEE_PANIC_ID_TEE_GETNEXTPERSISTENTOBJECT 0x00000A03UART_FR_RI (1 << 8)__va_list__ LIST_INSERT_AFTER(listelm,elm,field) do { QUEUEDEBUG_LIST_OP((listelm), field) if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) (listelm)->field.le_next->field.le_prev = &(elm)->field.le_next; (listelm)->field.le_next = (elm); (elm)->field.le_prev = &(listelm)->field.le_next; } while ( 0)MPIDR_AFF0_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)pl011_dev_alloc__ARM_FEATURE_SM3ARM32_CPSR_MODE_FIQ U(0x11)TEE_TYPE_ECDH_PUBLIC_KEY 0xA0000042PLATFORM_vexpress 1UINTMAX_C(v) UINT64_C(v)__FLT32_MIN_10_EXP__ (-37)TEE_PANIC_ID_TEE_BIGINTRELATIVEPRIME 0x00001B03TEE_ALG_GET_CHAIN_MODE(algo) (((algo) >> 8) & 0xF)TEE_TA_MANAGER_H dt_map_dev__FLT128_MIN_EXP__ (-16381)TAILQ_HEAD_INITIALIZER(head) { NULL, &(head).tqh_first }TAILQ_INSERT_AFTER(head,listelm,elm,field) do { QUEUEDEBUG_TAILQ_OP((listelm), field) if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL) (elm)->field.tqe_next->field.tqe_prev = &(elm)->field.tqe_next; else (head)->tqh_last = &(elm)->field.tqe_next; (listelm)->field.tqe_next = (elm); (elm)->field.tqe_prev = &(listelm)->field.tqe_next; } while ( 0)__STDC_UTF_32__ 1__INT_LEAST16_MAX__ 0x7fffTEE_ERROR_BAD_STATE 0xFFFF0007TEE_MATTR_CACHE_SHIFT U(12)TEE_PANIC_ID_TEE_MASKCANCELLATION 0x00000502CFG_RPMB_FS_DEV_ID 0CFG_TEE_API_VERSION GPD-1.1-devMIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1)SCTLR_A BIT32(1)TEE_ERROR_MAC_INVALID 0xFFFF3071TEE_TYPE_ECDSA_KEYPAIR 0xA1000041SPSR_64_MODE_SP_ELX U(0x1)WAIT_QUEUE_INITIALIZER { .slh_first = NULL }INTMAX_C(v) INT64_C(v)_CFG_WITH_SECURE_STORAGE 1TEE_ALG_GET_DIGEST_HASH(algo) __tee_alg_get_digest_hash(algo)__UINT16_TYPE__ short unsigned int__ARM_FEATURE_FMASCATTERED_ARRAY_DEFINE_ITEM(array_name,element_type) __SCT_ARRAY_DEF_ITEM1(array_name, 0, __COUNTER__, element_type)TEE_PANIC_ID_TEE_MACCOMPAREFINAL 0x00000F01__DRIVERS_SERIAL_H CFG_CRYPTO_CTR 1LLONG_MIN (-LLONG_MAX - 1LL)_T_SIZE_ UART_FR_RXFF (1 << 6)TA_FLAG_SECURE_DATA_PATH (1 << 5)TEE_PROPSET_CURRENT_CLIENT (TEE_PropSetHandle)0xFFFFFFFEUART_IMSC_RTIM (1 << 6)LIST_NEXT(elm,field) ((elm)->field.le_next)parms__FLT32X_HAS_INFINITY__ 1PRIu8 "u"__ssize_t_defined long intESR_ABT_WNR BIT32(6)FEAT_BTI_IMPLEMENTED ULL(0x1)TEE_ALG_CONCAT_KDF_SHA384_DERIVE_KEY 0x800050C1__UINT64_MAX__ 0xffffffffffffffffULTEE_ALG_HMAC_MD5 0x30000001INT_LEAST64_MAX INT64_MAXTEE_ALG_AES_CTS 0x10000310CPACR_EL1_FPEN_SHIFT U(20)__LDBL_DECIMAL_DIG__ 36LIST_INIT(head) do { (head)->lh_first = NULL; } while ( 0)TEE_ATTR_ECC_PRIVATE_VALUE 0xC0000341PRIxVA_WIDTH ((int)(sizeof(vaddr_t) * 2))__FLT16_MAX_EXP__ 16TA_PROP_STR_SINGLE_INSTANCE "gpd.ta.singleInstance"TEE_PANIC_ID_TEE_GENERATERANDOM 0x00001301TEE_PANIC_ID_TEE_MEMFILL 0x00000606false 0__FLT_MAX_EXP__ 128CFG_CRYPTOLIB_DIR core/lib/libtomcryptUART_DR 0x00__ATOMIC_SEQ_CST 5UART_LCRH_PEN (1 << 1)_GCC_SIZE_T TRACE_LEVELS_H TEE_ATTR_FLAG_VALUE (1 << 29)TEE_PANIC_ID_TEE_CHECKMEMORYACCESSRIGHTS 0x00000601_CFG_CORE_LTC_HASH 1SLIST_FOREACH_SAFE(var,head,field,tvar) for ((var) = SLIST_FIRST((head)); (var) && ((tvar) = SLIST_NEXT((var), field), 1); (var) = (tvar))dev_free__FLT32_MANT_DIG__ 24TEE_ALG_DES_CBC_MAC_NOPAD 0x30000111TEE_MATTR_GUARDED BIT(15)__DECLARE_KEEP_INIT1(sym,file_id) __DECLARE_KEEP_INIT2(sym, file_id)CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT)TCR_SHX_OSH U(0x2)__ARM_FEATURE_SVE2_AESTEE_HANDLE_FLAG_INITIALIZED 0x00020000__PRIPTR_PREFIX "l"TEE_TIME_MILLIS_BASE 1000__INTMAX_C(c) c ## LTEE_CRYPTO_ELEMENT_NONE 0x00000000ARM32_CPSR_MODE_UND U(0x1b)ESR_EC_DABT_EL0 U(0x24)__aligned(x) __attribute__((aligned(x)))CIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next)__need_ptrdiff_tCFG_DT 1RECURSIVE_MUTEX_INITIALIZER { .m = MUTEX_INITIALIZER, .owner = THREAD_ID_INVALID }CTR_L1IP_MASK U(0x3)PRIuPTR __PRIPTR_PREFIX "u"THREAD_EXCP_ALL (THREAD_EXCP_FOREIGN_INTR | THREAD_EXCP_NATIVE_INTR | (ARM32_CPSR_A >> ARM32_CPSR_F_SHIFT))TEE_PANIC_ID_TEE_AEDECRYPTFINAL 0x00001001TEE_PANIC_ID_TEE_RENAMEPERSISTENTOBJECT 0x00000904__GCC_IEC_559_COMPLEX 0DT_DRIVER_RSTCTRL__ARM_FEATURE_JCVTTEE_PANIC_ID_TEE_BIGINTCONVERTFROMOCTETSTRING 0x00001701TEE_CHAIN_MODE_GCM 0x8SIZE_8M UINTPTR_C(0x800000)__FLT16_HAS_QUIET_NAN__ 1_CFG_CORE_LTC_BIGNUM_MAX_BITS 4096TA_PROP_STR_MULTI_SESSION "gpd.ta.multiSession"PRIx16 "x"trace_printf_helper_raw(level,level_ok,...) trace_printf(NULL, 0, (level), (level_ok), __VA_ARGS__)__KERNEL_INTERRUPT_H ROUNDUP_OVERFLOW(v,size,res) (__extension__({ typeof(*(res)) __roundup_tmp = 0; typeof(v) __roundup_mask = (typeof(v))(size) - 1; ADD_OVERFLOW((v), __roundup_mask, &__roundup_tmp) ? 1 : (void)(*(res) = __roundup_tmp & ~__roundup_mask), 0; }))TEE_DES_BLOCK_SIZE 8ULTEE_DATA_FLAG_OVERWRITE 0x00000400__USER_LABEL_PREFIX__ CORE_MMU_USER_CODE_SIZE BIT(CORE_MMU_USER_CODE_SHIFT)UART_IMSC 0x38DEFINE_U32_REG_READWRITE_FUNCS(reg) DEFINE_U32_REG_READ_FUNC(reg) DEFINE_U32_REG_WRITE_FUNC(reg)_SIZE_T_DECLARED CIRCLEQ_FIRST(head) ((head)->cqh_first)TEE_PANIC_ID_TEE_CREATEPERSISTENTOBJECT 0x00000902CTR_DMINLINE_SHIFT U(16)TEE_COMMON_H __UINT_LEAST32_MAX__ 0xffffffffUCFG_OPTEE_REVISION_MINOR 16TEE_MAIN_ALGO_SM2_DSA_SM3 0x45TRACE_INFO 2__MM_FILE_H DAIF_D BIT32(9)MIDR_PRIMARY_PART_NUM_SHIFT U(4)PGT_SIZE (4 * 1024)__nex_bss TEE_MAIN_ALGO_SHA384 0x05__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1TEE_PANIC_ID_TEE_REALLOC 0x00000608TEE_OPERATION_DIGEST 5TEE_MMU_TYPES_H PLATFORM_FLAVOR qemu_armv8aCNTKCTL_PL0VCTEN BIT(1)__ptrESR_EC_ILLEGAL U(0x0e)__DEC_EVAL_METHOD__ 2TEE_PANIC_ID_TEE_BIGINTCONVERTFROMS32 0x00001702container_of(ptr,type,member) (__extension__({ const typeof(((type *)0)->member) *__ptr = (ptr); (type *)((unsigned long)(__ptr) - offsetof(type, member)); }))UART_FR_RTXDIS (1 << 13)TEE_ALG_SHA224 0x50000003TEE_ERROR_BUSY 0xFFFF000D__FLT32_MIN_EXP__ (-125)CPACR_EL1_FPEN_EL1 U(0x1)TEE_ATTR_ECC_EPHEMERAL_PUBLIC_VALUE_Y 0xD0000A46CONSOLE_BAUDRATE UART_BAUDRATETEE_STORAGE_PRIVATE_RPMB 0x80000100TEE_ALG_RSA_NOPAD 0x60000030TEE_PANIC_ID_TEE_BIGINTISPROBABLEPRIME 0x00001B02__DECIMAL_DIG__ 36UINT_FAST32_MAX UINT32_MAX__DBL_MIN_10_EXP__ (-307)TEE_ERROR_NOT_SUPPORTED 0xFFFF000ACFG_OPTEE_REVISION_MAJOR 3TEE_PANIC_ID_TEE_SETOPERATIONKEY2 0x00000C07ARM32_CPSR_I BIT(7)SPSR_32_E_MASK U(0x1)_GCC_PTRDIFF_T __FLT32X_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F32xINT32_MIN (-0x7fffffff-1)CFG_WITH_USER_TA 1__FLT_MIN_10_EXP__ (-37)SPSR_MODE_RW_64 U(0x0)__UINTPTR_TYPE__ long unsigned intHW_UNIQUE_KEY_WORD2 (HW_UNIQUE_KEY_WORD1 + 1)_CFG_CORE_LTC_CTS 1TEE_ERROR_BAD_PARAMETERS 0xFFFF0006__rodata_unpaged(x) __section(".rodata.__unpaged." x __SECTION_FLAGS_RODATA)TEE_ERROR_OVERFLOW 0xFFFF300FDEFINE_REG_WRITE_FUNC_(reg,type,asmreg) static inline __noprof void write_ ##reg(type val) { uint64_t val64 = val; asm volatile("msr " #asmreg ", %0" : : "r" (val64)); }__INT_FAST64_MAX__ 0x7fffffffffffffffL__DBL_MANT_DIG__ 53SPSR_32_T_MASK U(0x1)DEFINE_U64_REG_WRITE_FUNC(reg) DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg)__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)TEE_ALG_AES_CBC_MAC_NOPAD 0x30000110UART_CR_TXE (1 << 8)__INT_WCHAR_T_H TEE_PANIC_ID_TEE_BIGINTINITFMM 0x00001602TEE_PANIC_ID_TEE_DIGESTDOFINAL 0x00000D01CFG_CRYPTO_PBKDF2 1CLIDR_FIELD_WIDTH U(3)dt_device_matchSCATTERED_ARRAY_DEFINE_PG_ITEM(array_name,element_type) __SCT_ARRAY_DEF_PG_ITEM1(array_name, 0, __COUNTER__, element_type)CFG_SHMEM_START 0x42000000__INTPTR_MAX__ 0x7fffffffffffffffLTEE_ALG_DES_CBC_MAC_PKCS5 0x30000511__SIZEOF_LONG_DOUBLE__ 16DT_INFO_INVALID_REG ((paddr_t)-1)CFG_TEE_TA_LOG_LEVEL 1TEE_ALG_ECDSA_P384 0x70004041PRIi64 __PRI64_PREFIX "i"__size_t __WINT_MAX__ 0xffffffffU__SIZEOF_FLOAT__ 4TCR_SH1_SHIFT U(28)__FLT_EPSILON__ 1.19209289550781250000000000000000000e-7FCORTEX_A8_PART_NUM U(0xC08)TEE_PANIC_ID_TEE_GETPROPERTYASU32 0x00000208CFG_SECSTOR_TA 1TEE_TEXT_VA_START (TEE_RAM_VA_START + (TEE_LOAD_ADDR - TEE_RAM_START))TEE_ERROR_OUT_OF_MEMORY 0xFFFF000C__FLT64X_MIN_10_EXP__ (-4931)TEE_ERROR_EXCESS_DATA 0xFFFF0004TEE_PANIC_ID_TEE_COPYOBJECTATTRIBUTES 0x00000802__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1NSAPP_IDENTITY (NULL)QUEUEDEBUG_CIRCLEQ_HEAD(head,field) TEE_PANIC_ID_TEE_FREEPERSISTENTOBJECTENUMERATOR 0x00000A02tee_mtime_init() do { } while (0)__UINT8_C(c) cTEE_ATTR_ECC_PUBLIC_VALUE_X 0xD0000141MSG_RAW(...) trace_printf_helper_raw(0, false, __VA_ARGS__)__ARM_FEATURE_NUMERIC_MAXMIN__ARM_ARCH_8A 1GICD_BASE (GIC_BASE + GICD_OFFSET)pl011_dataTEE_ATTR_HKDF_IKM 0xC00001C0TEE_MATTR_PRX (TEE_MATTR_PR | TEE_MATTR_PX)TEE_MATTR_PRWX (TEE_MATTR_PRW | TEE_MATTR_PX)phys_ddr_overall_compat_end SCATTERED_ARRAY_END(phys_ddr_overall_compat, struct core_mmu_phys_mem)__INTMAX_TYPE__ long intTEE_STORAGE_PRIVATE 0x00000001va_copy(d,s) __builtin_va_copy(d,s)CFG_WITH_STACK_CANARIES 1INT_FAST32_MIN INT32_MINTEE_ALG_ECDH_P384 0x80004042__DECLARE_KEEP_INIT2(sym,file_id) extern const unsigned long ____keep_init_ ##sym ##file_id; const unsigned long ____keep_init_ ##sym ##_ ##file_id __section("__keep_meta_vars_init") = (unsigned long)&(sym)TCR_SH0_SHIFT U(12)TEE_ATTR_BIT_VALUE TEE_ATTR_FLAG_VALUEunsigned charCFG_CRYPTOLIB_NAME_tomcrypt 1__ARM_FEATURE_QRDMXUART_CR_RTSEN (1 << 14)CFG_CRYPTO_CTS 1DT_DRIVER_CLKTEE_PANIC_ID_TEE_CIPHERINIT 0x00000E02__ORDER_LITTLE_ENDIAN__ 1234_PTRDIFF_T_DECLARED CIRCLEQ_LOOP_NEXT(head,elm,field) (((elm)->field.cqe_next == (void *)(head)) ? ((head)->cqh_first) : (elm->field.cqe_next))LIST_ENTRY(type) struct { struct type *le_next; struct type **le_prev; }UART_FBRD 0x28__LONG_WIDTH__ 64DEFINE_U64_REG_READ_FUNC(reg) DEFINE_REG_READ_FUNC_(reg, uint64_t, reg)TEE_ERROR_TIME_NEEDS_RESET 0xFFFF5001SCTLR_SPAN BIT32(23)STAILQ_NEXT(elm,field) ((elm)->field.stqe_next)__FLT_DIG__ 6__SCHAR_MAX__ 0x7fTEE_ALG_CONCAT_KDF_SHA1_DERIVE_KEY 0x800020C1TEE_PANIC_ID_TEE_BIGINTSHIFTRIGHT 0x00001805CORE_MMU_USER_PARAM_SIZE BIT(CORE_MMU_USER_PARAM_SHIFT)__DBL_MAX_EXP__ 1024TEE_ECC_CURVE_NIST_P521 0x00000005TEE_ATTR_BIT_PROTECTED TEE_ATTR_FLAG_PUBLIC__UINT_LEAST16_MAX__ 0xffffTEE_MAIN_ALGO_DES 0x11SIMPLEQ_INSERT_TAIL(head,elm,field) do { (elm)->field.sqe_next = NULL; *(head)->sqh_last = (elm); (head)->sqh_last = &(elm)->field.sqe_next; } while ( 0)TA_PROP_STR_KEEP_ALIVE "gpd.ta.instanceKeepAlive"__ARM_FEATURE_FP16_FML__FLT32X_MAX_EXP__ 1024__bss __section(".bss")__SIG_ATOMIC_MAX__ 0x7fffffffFMSG(...) (void)0CFG_SECSTOR_TA_MGMT_PTA 1__FLT32_MAX__ 3.40282346638528859811704183484516925e+38F32TTBR_ASID_SHIFT U(48)TEE_ECC_CURVE_NIST_P192 0x00000001CORE_MMU_BASE_TABLE_OFFSET (CFG_TEE_CORE_NB_CORE * BIT(CFG_LPAE_ADDR_SPACE_BITS - CORE_MMU_BASE_TABLE_SHIFT) * U(8))_PTRDIFF_T TEE_ALG_RSASSA_PKCS1_V1_5 0xF0000830_CFG_CORE_LTC_CIPHER 1__FLT64X_MAX__ 1.18973149535723176508575932662800702e+4932F64x__PTRDIFF_WIDTH__ 64VM_FLAG_PERMANENT BIT(1)_out_arm_include_generated_conf_h_ SHRT_MIN (-SHRT_MAX - 1)IT_CONSOLE_UART IT_UART1TEE_ATTR_DSA_PRIVATE_VALUE 0xC0000231__SCATTERED_ARRAY_H TEE_U16_BSWAP(x) __compiler_bswap16((x))CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head))VM_FLAGS_NONPRIV (VM_FLAG_EPHEMERAL | VM_FLAG_PERMANENT | VM_FLAG_SHAREABLE)TEE_ALG_AES_CBC_MAC_PKCS5 0x30000510SLIST_HEAD_INITIALIZER(head) { NULL }INTPTR_MAX LONG_MAX__FLT64X_NORM_MAX__ 1.18973149535723176508575932662800702e+4932F64xINT16_MAX 0x7fffTEE_TYPE_HMAC_SHA1 0xA0000002HW_UNIQUE_KEY_WORD1 (8)TAILQ_CONCAT(head1,head2,field) do { if (!TAILQ_EMPTY(head2)) { *(head1)->tqh_last = (head2)->tqh_first; (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; (head1)->tqh_last = (head2)->tqh_last; TAILQ_INIT((head2)); } } while ( 0)TEE_U16_FROM_BIG_ENDIAN(x) TEE_U16_BSWAP(x)STAILQ_HEAD_INITIALIZER(head) { NULL, &(head).stqh_first }ESR_EC_AARCH64_SYS U(0x18)__UINT_LEAST64_TYPE__ long unsigned intSTAILQ_CONCAT(head1,head2) do { if (!STAILQ_EMPTY((head2))) { *(head1)->stqh_last = (head2)->stqh_first; (head1)->stqh_last = (head2)->stqh_last; STAILQ_INIT((head2)); } } while ( 0)tee_mtime_stamp(descr) do { } while (0)MPIDR_AFFINITY_BITS U(8)TEE_ALG_RSAES_PKCS1_OAEP_MGF1_SHA512 0x60610230ULLONG_MAX (LLONG_MAX * 2ULL + 1ULL)MALLOC_INITIAL_POOL_MIN_SIZE 1024__SIZEOF_LONG_LONG__ 8__ARM_FEATURE_SVE_BITSPRId8 "d"PRIo16 "o"TEE_ALG_PBKDF2_HMAC_SHA1_DERIVE_KEY 0x800020C2UART_IBRD 0x24__FLT64X_MAX_10_EXP__ 4932STDLIB_H __FLT32_DECIMAL_DIG__ 9ESR_EC_BREAKPT_EL0 U(0x30)UART_FR_BUSY (1 << 3)CTR_DMINLINE_WIDTH U(4)TEE_ATTR_RSA_COEFFICIENT 0xC0000830PRIX32 "X"TRACE_FLOW 4TEE_ALG_AES_CTR 0x10000210__ARM_ARCH_PROFILE 65_WCHAR_T_DEFINED_ TEE_ATTR_RSA_PSS_SALT_LENGTH 0xF0000A30UART_CR_RXE (1 << 9)CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1)__WINT_TYPE__ unsigned intTEE_LOGIN_APPLICATION_USER 0x00000005__FLT128_MAX_10_EXP__ 4932TEE_ALG_HMAC_SHA384 0x30000005TEE_MAIN_ALGO_RSA 0x30_CFG_CORE_LTC_DES 1TCR_XRGNX_WT U(0x2)GICC_OFFSET 0x10000probeUART_DMAWM 0x08TEE_ERROR_CORRUPT_OBJECT_2 0xF0100002TEE_PANIC_ID_TEE_CLOSEOBJECT 0x00000701CNTKCTL_PL0PCTEN BIT(0)TEE_PANIC_ID_TEE_GETOBJECTBUFFERATTRIBUTE 0x00000702CFG_TA_MBEDTLS_MPI 1TEE_MAIN_ALGO_SHA1 0x02__FLT_MANT_DIG__ 24CONDVAR_INITIALIZER { .m = NULL }CHAR_BIT __CHAR_BIT__TEE_OPERATION_STATE_ACTIVE 0x00000001ESR_EC_AARCH32_FP U(0x28)CORE_MMU_USER_CODE_SHIFT SMALL_PAGE_SHIFT__va_copy(d,s) __builtin_va_copy(d,s)QUEUEDEBUG_TAILQ_OP(elm,field) __FLT64_HAS_QUIET_NAN__ 1UINT64_MAX 0xffffffffffffffffULPRIoPTR __PRIPTR_PREFIX "o"va_end(v) __builtin_va_end(v)DT_INFO_INVALID_RESET -1_CFG_CORE_LTC_DSA 1CORTEX_A9_PART_NUM U(0xC09)ESR_EC_BREAKPT_EL1 U(0x31)TEE_ALG_HMAC_SHA256 0x30000004TEE_ATTR_FLAG_PUBLIC (1 << 28)TEE_SM4_BLOCK_SIZE 16UL__ARM_FEATURE_SVE_MATMUL_FP32LIST_INSERT_HEAD(head,elm,field) do { QUEUEDEBUG_LIST_INSERT_HEAD((head), (elm), field) if (((elm)->field.le_next = (head)->lh_first) != NULL) (head)->lh_first->field.le_prev = &(elm)->field.le_next; (head)->lh_first = (elm); (elm)->field.le_prev = &(head)->lh_first; } while ( 0)_TAILQ_HEAD(name,type,qual) struct name { qual type *tqh_first; qual type *qual *tqh_last; }_TAILQ_ENTRY(type,qual) struct { qual type *tqe_next; qual type *qual *tqe_prev; }CFG_CORE_WORKAROUND_SPECTRE_BP 1__SIZE_WIDTH__ 64phys_mem_map_begin SCATTERED_ARRAY_BEGIN(phys_mem_map, struct core_mmu_phys_mem)__SIZEOF_PADDR__ __SIZEOF_POINTER__SIZE_2M UINTPTR_C(0x200000)CFG_CRYPTO_SHA224 1__ARM_FEATURE_MEMORY_TAGGING_WCHAR_T_H __INT_LEAST8_MAX__ 0x7fSIMPLEQ_HEAD(name,type) struct name { struct type *sqh_first; struct type **sqh_last; }TEE_ALG_SM3 0x50000007__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__TEE_MAC_SIZE_AES_CMAC TAILQ_INSERT_TAIL(head,elm,field) do { QUEUEDEBUG_TAILQ_INSERT_TAIL((head), (elm), field) (elm)->field.tqe_next = NULL; (elm)->field.tqe_prev = (head)->tqh_last; *(head)->tqh_last = (elm); (head)->tqh_last = &(elm)->field.tqe_next; } while ( 0)_CFG_CORE_LTC_SHA256 1TEE_NUM_PARAMS 4__FLT_RADIX__ 2__INT32_C(c) cTEE_TYPE_SM2_KEP_KEYPAIR 0xA1000046_ANSI_STDARG_H_ __SIZEOF_WCHAR_T__ 4__FLT32X_DIG__ 15CLIDR_LOUIS_SHIFT U(21)TEE_ATTR_HKDF_SALT 0xD00002C0STACK_ALIGNMENT 64INT_LEAST64_MIN INT64_MINTEE_MAIN_ALGO_SHA512 0x06ARM32_CPSR_IT_MASK2 U(0x0000fc00)__FLT_EVAL_METHOD_TS_18661_3__ 0__maybe_unused __attribute__((unused))TEE_ORIGIN_TEE 0x00000003PRIxUA PRIxPTRUART_BAUDRATE 115200CFG_EARLY_TA_COMPRESS 1compat_dataTEE_PANIC_ID_TA_DESTROYENTRYPOINT 0x00000103TEE_ALG_AES_XTS 0x10000410TCR_IRGN1_SHIFT U(24)CFG_CRYPTO_DES 1TEE_PANIC_ID_TEE_TRUNCATEOBJECTDATA 0x00000B03TEE_DATA_FLAG_ACCESS_WRITE_META 0x00000004STAILQ_REMOVE(head,elm,type,field) do { if ((head)->stqh_first == (elm)) { STAILQ_REMOVE_HEAD((head), field); } else { struct type *curelm = (head)->stqh_first; while (curelm->field.stqe_next != (elm)) curelm = curelm->field.stqe_next; if ((curelm->field.stqe_next = curelm->field.stqe_next->field.stqe_next) == NULL) (head)->stqh_last = &(curelm)->field.stqe_next; } } while ( 0)LIST_HEAD(name,type) struct name { struct type *lh_first; }TEE_DATA_FLAG_ACCESS_READ 0x00000001__rodata_dummy __section(".rodata.dummy" __SECTION_FLAGS_RODATA)TEE_ALG_RSAES_PKCS1_OAEP_MGF1_SHA224 0x60310230SCATTERED_ARRAY_FOREACH(elem,array_name,element_type) for ((elem) = SCATTERED_ARRAY_BEGIN(array_name, element_type); (elem) < SCATTERED_ARRAY_END(array_name, element_type); (elem)++)__FLT32X_MANT_DIG__ 53__ATOMIC_H UART_FR_DSR (1 << 1)__UINT_FAST8_TYPE__ unsigned charINT8_C(v) v__CHAR32_TYPE__ unsigned intMB_LEN_MAX 1__INT_WIDTH__ 32TEE_PANIC_ID_TEE_CLOSEANDDELETEPERSISTENTOBJECT 0x00000901__UINT64_TYPE__ long unsigned intDEFINE_DT_DRIVER(name) SCATTERED_ARRAY_DEFINE_PG_ITEM(dt_drivers, struct dt_driver)ULONG_MAX (LONG_MAX * 2UL + 1UL)CFG_CRYPTO_DSA 1DT_STATUS_OK_SEC BIT(1)INT_LEAST32_MAX INT32_MAXUART_MIS 0x40TEE_PARAM_TYPE_MEMREF_INOUT 7SPSR_32_T_SHIFT U(5)INT_FAST64_MAX INT64_MAXTEE_ERROR_STORAGE_NOT_AVAILABLE_2 0xF0100004TEE_PARAM_TYPE_NONE 0TZDRAM_BASE CFG_TZDRAM_START__LP64__ 1TEE_HANDLE_FLAG_PERSISTENT 0x00010000ESR_EC_IABT_EL0 U(0x20)TEE_PANIC_ID_TEE_CLOSEANDDELETEPERSISTENTOBJECT1 0x00000905INT32_C(v) vTEE_ALG_SM4_ECB_NOPAD 0x10000014TEE_TYPE_SM2_PKE_PUBLIC_KEY 0xA0000047MUTEX_INITIALIZER { .wq = WAIT_QUEUE_INITIALIZER }CFG_EARLY_TA 1SMALL_PAGE_SHIFT U(12)TEE_PANIC_ID_TA_OPENSESSIONENTRYPOINT 0x00000105__FILE_ID__ core_drivers_pl011_c__FLT32X_DECIMAL_DIG__ 17TEE_PARAM_TYPE_VALUE_OUTPUT 2TEE_ATTR_DH_SUBPRIME 0xD0001132__GCC_ATOMIC_CHAR32_T_LOCK_FREE 2va_arg(v,l) __builtin_va_arg(v,l)__INT16_TYPE__ short int__FLT128_DIG__ 33serial_driverTEE_RAM_START TZDRAM_BASESTAILQ_FIRST(head) ((head)->stqh_first)TEE_OPERATION_CIPHER 1CORE_MMU_BASE_TABLE_LEVEL U(1)CFG_CORE_DYN_SHM 1UART_FR_DDCD (1 << 11)__INT_FAST32_TYPE__ long int___int_size_t_h TEE_MATTR_PW BIT(5)TAILQ_FOREACH_REVERSE_SAFE(var,head,headname,field,prev) for ((var) = TAILQ_LAST((head), headname); (var) && ((prev) = TAILQ_PREV((var), headname, field), 1); (var) = (prev))_SIZE_T_DEFINED_ ESR_EC_AARCH64_FP U(0x2c)TEE_PANIC_ID_TEE_ALLOCATEPERSISTENTOBJECTENUMERATOR 0x00000A01size_t_DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H __GCC_ATOMIC_LONG_LOCK_FREE 2__ARM_FEATURE_SVE_MATMUL_FP64CFG_TEE_CORE_NB_CORE 4CORTEX_A73_PART_NUM U(0xD09)INTPTR_MIN LONG_MINoffsCFG_SYSTEM_PTA 1__section(x) __attribute__((section(x)))__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1GICC_BASE (GIC_BASE + GICC_OFFSET)TEE_ALG_DSA_SHA256 0x70004131INT_FAST16_MIN INT16_MINESR_EC_IABT_EL1 U(0x21)_CFG_CORE_LTC_SHA224 1NULLbaud_rateTEE_ERROR_BAD_FORMAT 0xFFFF0005STAILQ_FOREACH(var,head,field) for ((var) = ((head)->stqh_first); (var); (var) = ((var)->field.stqe_next))MAX_PRINT_SIZE 256CIRCLEQ_INSERT_HEAD(head,elm,field) do { QUEUEDEBUG_CIRCLEQ_HEAD((head), field) (elm)->field.cqe_next = (head)->cqh_first; (elm)->field.cqe_prev = (void *)(head); if ((head)->cqh_last == (void *)(head)) (head)->cqh_last = (elm); else (head)->cqh_first->field.cqe_prev = (elm); (head)->cqh_first = (elm); } while ( 0)__noprof __attribute__((no_instrument_function))pl011_flushCFG_PL011 1DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | DAIFBIT_ABT | DAIFBIT_DBG)__WCHAR_MIN__ 0UTEE_PANIC_ID_TEE_READOBJECTDATA 0x00000B01TEE_PANIC_ID_TEE_GETPROPERTYASIDENTITY 0x00000206__compiler_atomic_load(p) __atomic_load_n((p), __ATOMIC_RELAXED)TEE_MAIN_ALGO_ECDSA 0x41TEE_ATTR_DSA_PUBLIC_VALUE 0xD0000131UINTPTR_C(v) UL(v)TEE_PANIC_ID_TEE_GETPROPERTYASSTRING 0x00000207_GCC_WCHAR_T SPSR_64_MODE_EL1 U(0x1)TEE_ALG_ECDSA_P521 0x70005041KERNEL_PANIC_H __uint32_t_defined TEE_ALG_ECDH_P224 0x80002042ESR_FSC_ACCF_L2 U(0x0a)TEE_MEM_OUTPUT 0x00000002__INT_FAST64_WIDTH__ 64__LDBL_MIN__ 3.36210314311209350626267781732175260e-4932LTEE_MAC_SIZE_AES_CBC_MAC_NOPAD tee_vbuf_is_non_sec(buf,len) core_vbuf_is(CORE_MEM_NON_SEC, (void *)(buf), (len))nex_realloc(ptr,size) realloc(ptr, size)addrhave_rx_data____keep_pager_pl011_ops_core_drivers_pl011_cTEE_ALG_AES_CCM 0x40000710va_start(v,l) __builtin_va_start(v,l)__FLT16_MIN_10_EXP__ (-4)CFG_TEE_MANUFACTURER LINARO__CHAR_UNSIGNED__ 1dt_driver_typeUINT8_MAX 0xffTEE_API_DEFINES_EXTENSIONS_H __LDBL_MIN_EXP__ (-16381)PGT_NUM_PGT_PER_PAGE 1_BSD_WCHAR_T_TEE_RAM_VA_START TEE_RAM_STARTCFG_CRYPTO_AES 1__GCC_HAVE_DWARF2_CFI_ASM 1HW_UNIQUE_KEY_WORD4 (HW_UNIQUE_KEY_WORD1 + 3)phys_ddr_overall_begin SCATTERED_ARRAY_BEGIN(phys_ddr_overall, struct core_mmu_phys_mem)_SIZE_T_ CFG_UNWIND 1TEE_TYPE_SM4 0xA0000014IRQ_TYPE_NONE 0__FLT16_MAX_10_EXP__ 4TEE_ALG_HMAC_SHA224 0x30000003CFG_TA_BGET_TEST 1TEE_DATA_FLAG_ACCESS_WRITE 0x00000002__need_size_tTA_FLAG_MULTI_SESSION (1 << 3)CFG_FTRACE_BUF_WHEN_FULL shiftKERNEL_VFP_H __FLT64X_MAX_EXP__ 16384LIST_INSERT_BEFORE(listelm,elm,field) do { QUEUEDEBUG_LIST_OP((listelm), field) (elm)->field.le_prev = (listelm)->field.le_prev; (elm)->field.le_next = (listelm); *(listelm)->field.le_prev = (elm); (listelm)->field.le_prev = &(elm)->field.le_next; } while ( 0)TEE_ALG_ECDH_P521 0x80005042__INT16_MAX__ 0x7fffMPIDR_CLUSTER_MASK MPIDR_AFF1_MASKVM_FLAG_EPHEMERAL BIT(0)__KERNEL_TS_MANAGER_H _CFG_CORE_LTC_ASN1 1INT_MAX __INT_MAX___CFG_CORE_LTC_CMAC 1TEE_ATTR_DH_X_BITS 0xF0001332ESR_FSC_ACCF_L3 U(0x0b)TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA256 0x70414930TEE_ATTR_DSA_PRIME 0xD0001031ESR_EC_AARCH64_SVC U(0x15)PRIxPTR __PRIPTR_PREFIX "x"__packed __attribute__((packed))UART_RSR_ECR 0x04CFG_TA_ASLR 1TEE_PANIC_ID_TEE_SEEKOBJECTDATA 0x00000B02PRIx64 __PRI64_PREFIX "x"__FLT_HAS_QUIET_NAN__ 1__ARM_FEATURE_SM4TEE_MATTR_VALID_BLOCK BIT(0)TEE_ALG_ECDSA_P224 0x70002041QUEUEDEBUG_TAILQ_INSERT_HEAD(head,elm,field) __SCT_ARRAY_DEF_ITEM1(array_name,order,id,element_type) __SCT_ARRAY_DEF_ITEM2(array_name, order, id, element_type)SCTLR_I BIT32(12)TEE_PANIC_ID_TEE_BIGINTMOD 0x00001A03UART_LCR_H 0x2CUTIL_H CFG_CRYPTO_DH 1SPSR_64_MODE_EL0 U(0x0)CFG_TEE_CORE_TA_TRACE 1INT_LEAST8_MAX INT8_MAX__FLT64_HAS_INFINITY__ 1UART_FR_DCTS (1 << 9)TEE_SUCCESS 0x00000000SLIST_REMOVE_HEAD(head,field) do { (head)->slh_first = (head)->slh_first->field.sle_next; } while ( 0)TEE_TYPE_DATA 0xA00000BF_T_WCHAR_ __SCHAR_WIDTH__ 8QUEUEDEBUG_LIST_POSTREMOVE(elm,field) TCR_EPD0 BIT32(7)TEE_ERROR_ACCESS_DENIED 0xFFFF0001__ORDER_PDP_ENDIAN__ 3412TRACE_LEVEL 3MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM_RWTEE_ATTR_DH_PUBLIC_VALUE 0xD0000132TEE_MATTR_UW BIT(8)SCATTERED_ARRAY_END(array_name,element_type) (__extension__({ static const element_type __scattered_array_end[0] __unused __section(".scattered_array_" #array_name "_2" __SECTION_FLAGS_RODATA); __scattered_array_end; }))CTR_IMINLINE_MASK U(0xf)TEE_HANDLE_FLAG_EXPECT_TWO_KEYS 0x00080000__SCT_ARRAY_DEF_PG_ITEM1(array_name,order,id,element_type) __SCT_ARRAY_DEF_PG_ITEM2(array_name, order, id, element_type)TEE_PANIC_ID_TEE_BIGINTDIV 0x00001902__WINT_WIDTH__ 32TEE_MEMORY_ACCESS_READ 0x00000001TEE_ERROR_CORRUPT_OBJECT 0xF0100001CFG_CRYPTO_SM2_PKE 1CFG_DTB_MAX_SIZE 0x100000TEE_ORIGIN_TRUSTED_APP 0x00000004ITRF_TRIGGER_LEVEL BIT(0)_panic0() __panic((void *)0)TEE_MEMREF_2_USED 0x00000004SPSR_32_T_ARM U(0x0)IMSG(...) trace_printf_helper(TRACE_INFO, true, __VA_ARGS__)PRIiPTR __PRIPTR_PREFIX "i"TEE_ALG_HKDF_SHA1_DERIVE_KEY 0x800020C0__scattered_array_0dt_drivers__FLT16_MANT_DIG__ 11LONG_MAX __LONG_MAX__INT16_C(v) v__INTMAX_WIDTH__ 64TEE_PANIC_ID_TEE_RESTRICTOBJECTUSAGE 0x00000705SPSR_MODE_RW_32 U(0x1)__GNUC_VA_LIST CFG_WITH_LPAE 1TEE_USAGE_DECRYPT 0x00000004pl011_dev_freeTEE_USAGE_MAC 0x00000008MALLOC_H __INT_LEAST64_WIDTH__ 64CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT & CPACR_EL1_FPEN_MASK)tee_mtime_report() do { } while (0)GIC_BASE 0x08000000_CFG_CORE_LTC_CCM 1__aarch64__ 1CFG_ARM64_ldelf 1__ATOMIC_RELAXED 0__UINTMAX_MAX__ 0xffffffffffffffffUL__must_check __attribute__((warn_unused_result))CFG_RPMB_FS_RD_ENTRIES 8TA_RAM_SIZE (ROUNDDOWN(TZDRAM_BASE + (TZDRAM_SIZE - TEE_SDP_TEST_MEM_SIZE), SMALL_PAGE_SIZE) - TA_RAM_START)UART_RIS 0x3CTEE_ORIGIN_COMMS 0x00000002TA_PROP_STR_VERSION "gpd.ta.version"_CFG_CORE_LTC_SHA512_256 1STAILQ_EMPTY(head) ((head)->stqh_first == NULL)TEE_CHAIN_MODE_CCM 0x7HW_UNIQUE_KEY_WORD3 (HW_UNIQUE_KEY_WORD1 + 2)TEE_MAIN_ALGO_SM3 0x07__deprecated __attribute__((deprecated))TEE_MAIN_ALGO_SM4 0x14INT16_MIN (-0x7fff-1)MPIDR_AFFLVL_MASK U(0xff)UART_IFLS 0x34__DBL_DENORM_MIN__ ((double)4.94065645841246544176568792868221372e-324L)GENMASK_64(h,l) (((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h))))__GCC_IEC_559 0pl011_getcharTEE_ALG_GET_INTERNAL_HASH(algo) (((algo) >> 20) & 0x7)TAILQ_INSERT_BEFORE(listelm,elm,field) do { QUEUEDEBUG_TAILQ_OP((listelm), field) (elm)->field.tqe_prev = (listelm)->field.tqe_prev; (elm)->field.tqe_next = (listelm); *(listelm)->field.tqe_prev = (elm); (listelm)->field.tqe_prev = &(elm)->field.tqe_next; } while ( 0)TEE_ALG_CONCAT_KDF_SHA256_DERIVE_KEY 0x800040C1_CFG_CORE_LTC_MPI 1TEE_ALG_SHA384 0x50000005INT64_MAX 0x7fffffffffffffffLio_read32register_phys_mem_pgdir(type,addr,size) register_phys_mem(type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), ROUNDUP(size + addr - ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), CORE_MMU_PGDIR_SIZE))SLIST_ENTRY(type) struct { struct type *sle_next; }phys_sdp_mem_begin SCATTERED_ARRAY_BEGIN(phys_sdp_mem, struct core_mmu_phys_mem)TEE_ALG_HKDF_SHA512_DERIVE_KEY 0x800060C0MAX(a,b) (__extension__({ __typeof__(a) _a = (a); __typeof__(b) _b = (b); _a > _b ? _a : _b; }))LIST_HEAD_INITIALIZER(head) { NULL }TEE_MATTR_UX BIT(9)IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)UART_LCRH_STP2 (1 << 3)__INT_FAST16_MAX__ 0x7fffffffffffffffLCFG_CORE_ASLR 1INT_LEAST16_MAX INT16_MAXLONG_MIN (-LONG_MAX - 1L)TCR_ORGN1_SHIFT U(26)MPIDR_CLUSTER_SHIFT MPIDR_AFF1_SHIFTCOMPILER_H MPIDR_AFF1_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)TEE_PANIC_ID_TEE_AEUPDATEAAD 0x00001005_WCHAR_T_DECLARED CFG_CORE_WORKAROUND_SPECTRE_BP_SEC 1__ATOMIC_RELEASE 3__INT64_MAX__ 0x7fffffffffffffffLTEE_TIME_ADD(t1,t2,dst) do { (dst).seconds = (t1).seconds + (t2).seconds; (dst).millis = (t1).millis + (t2).millis; if ((dst).millis >= TEE_TIME_MILLIS_BASE) { (dst).seconds++; (dst).millis -= TEE_TIME_MILLIS_BASE; } } while (0)STAILQ_INSERT_HEAD(head,elm,field) do { if (((elm)->field.stqe_next = (head)->stqh_first) == NULL) (head)->stqh_last = &(elm)->field.stqe_next; (head)->stqh_first = (elm); } while ( 0)tee_pbuf_is_sec(buf,len) core_pbuf_is(CORE_MEM_SEC, (paddr_t)(buf), (len))__INT_LEAST8_WIDTH__ 8__GNUC__ 10TEE_MEMORY_ACCESS_WRITE 0x00000002__DBL_DECIMAL_DIG__ 17__INT_FAST32_WIDTH__ 64__int8_t_defined CFG_RPMB_FS_CACHE_ENTRIES 0DEFINE_U32_REG_READ_FUNC(reg) DEFINE_REG_READ_FUNC_(reg, uint32_t, reg)QUEUEDEBUG_TAILQ_INSERT_TAIL(head,elm,field) TCR_T1SZ_SHIFT U(16)__AARCH64_CMODEL_TINY____INT_LEAST32_WIDTH__ 32ARM32_CPSR_MODE_ABT U(0x17)__FLT32X_NORM_MAX__ 1.79769313486231570814527423731704357e+308F32xdivisorDT_DRIVER_UART__FLT128_HAS_DENORM__ 1ESR_EC_SOFTSTP_EL1 U(0x33)TEE_PANIC_ID_TEE_RESETTRANSIENTOBJECT 0x00000808TEE_PANIC_ID_TEE_BIGINTSUB 0x00001906TEE_LOGIN_REE_KERNEL 0x80000000__SCT_ARRAY_DEF_PG_ITEM2(array_name,order,id,element_type) __SCT_ARRAY_DEF_PG_ITEM3(element_type, __scattered_array_ ## id ## array_name, ".scattered_array_" #array_name "_1_" #order)TEE_HANDLE_FLAG_KEY_SET 0x00040000SPSR_64(el,sp,daif) (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT)TEE_LOAD_ADDR TEE_RAM_STARTTEE_ALG_DH_DERIVE_SHARED_SECRET 0x80000032__FLT64X_MIN__ 3.36210314311209350626267781732175260e-4932F64xPRId32 "d"__INT_MAX__ 0x7fffffffTEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA384 0x70515930TEE_ALG_DSA_SHA1 0x70002131__GXX_ABI_VERSION 1014__INT_LEAST8_TYPE__ signed charVM_FLAG_LDELF BIT(3)TAILQ_NEXT(elm,field) ((elm)->field.tqe_next)CIRCLEQ_LAST(head) ((head)->cqh_last)SPSR_64_MODE_SP_EL0 U(0x0)_WCHAR_T TEE_ALG_AES_ECB_NOPAD 0x10000010TEE_ATTR_SM2_ID_RESPONDER 0xD0000546UINT8_C(v) vCFG_CRYPTO_RSASSA_NA1 1TEE_PANIC_ID_TEE_OPENTASESSION 0x00000403TEE_LOGIN_PUBLIC 0x00000000SPSR_32_E_LITTLE U(0x0)__FLT_EVAL_METHOD__ 0__UINT_FAST64_TYPE__ long unsigned intCFG_ENABLE_EMBEDDED_TESTS 1__INT8_MAX__ 0x7fSIMPLEQ_INSERT_HEAD(head,elm,field) do { if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) (head)->sqh_last = &(elm)->field.sqe_next; (head)->sqh_first = (elm); } while ( 0)TEE_MEMREF_1_USED 0x00000002_WCHAR_T_ __ATOMIC_ACQUIRE 2INT8_MIN (-0x7f-1)SHIFT_U32(v,shift) ((uint32_t)(v) << (shift))serial_chipCFG_TA_FLOAT_SUPPORT 1read_ctr() read_ctr_el0()VFP_NUM_REGS U(32)QUEUEDEBUG_CIRCLEQ_POSTREMOVE(elm,field) register_ddr(addr,size) __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), phys_ddr_overall)__PIC__ 1__DECLARE_KEEP_PAGER2(sym,file_id) extern const unsigned long ____keep_pager_ ##sym; const unsigned long ____keep_pager_ ##sym ##_ ##file_id __section("__keep_meta_vars_pager") = (unsigned long)&(sym)ESR_FSC_SIZE_L2 U(0x02)_SYS_SIZE_T_H PLATFORM_FLAVOR_qemu_armv8a 1ESR_FSC_TRANS_L2 U(0x06)TAILQ_PREV(elm,headname,field) (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))WRITE_ONCE(p,v) __compiler_atomic_store(&(p), (v))IMSG_RAW(...) trace_printf_helper_raw(TRACE_INFO, true, __VA_ARGS__)assert(expr) do { if (!(expr)) { _assert_log(#expr, __FILE__, __LINE__, __func__); _assert_break(); } } while (0)DAIFBIT_DBG BIT32(3)DAIFBIT_ABT BIT32(2)__ILP32__TEE_ATTR_DSA_SUBPRIME 0xD0001131SCATTERED_ARRAY_BEGIN(array_name,element_type) (__extension__({ static const element_type __scattered_array_begin[0] __unused __section(".scattered_array_" #array_name "_0" __SECTION_FLAGS_RODATA); (const element_type *)scattered_array_relax_ptr( __scattered_array_begin); }))pbaseTCR_SHX_ISH U(0x3)SLIST_FIRST(head) ((head)->slh_first)TEE_ERROR_SECURITY 0xFFFF000FUINT_FAST16_MAX UINT16_MAXTA_FLAG_CONCURRENT (1 << 8)PRIx32 "x"PRIxVA PRIxPTR__ARM_FEATURE_TMECFG_SM_NO_CYCLE_COUNTING 1TEE_PANIC_ID_TEE_BIGINTINITFMMCONTEXT 0x00001603DT_DRIVER_NOTYPESIMPLEQ_INSERT_AFTER(head,listelm,elm,field) do { if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL) (head)->sqh_last = &(elm)->field.sqe_next; (listelm)->field.sqe_next = (elm); } while ( 0)CORE_MEMPROT_H TEE_ATTR_PBKDF2_SALT 0xD00002C2DAIF_F BIT32(6)UART_FR_DDSR (1 << 10)TEE_MAIN_ALGO_SHA256 0x04__SIZEOF_SIZE_T__ 8TEE_ERROR_NOT_IMPLEMENTED 0xFFFF0009CFG_CRYPTO 1CFG_CRYPTO_SIZE_OPTIMIZATION 1TEE_ALG_HMAC_SHA512 0x30000006PRIX8 "X"CORE_MMU_USER_CODE_MASK ((paddr_t)CORE_MMU_USER_CODE_SIZE - 1)TAILQ_EMPTY(head) ((head)->tqh_first == NULL)MPIDR_AFF0_SHIFT U(0)UART_IMSC_RXIM (1 << 4)TCR_EL1_IPS_SHIFT U(32)__need_NULLoffsetof(TYPE,MEMBER) __builtin_offsetof (TYPE, MEMBER)TEE_HANDLE_NULL 0TEE_ATTR_RSA_EXPONENT1 0xC0000630putcTEE_TYPE_HMAC_SHA384 0xA0000005TEE_MATTR_PRW (TEE_MATTR_PR | TEE_MATTR_PW)IS_POWER_OF_TWO(x) (((x) != 0) && (((x) & (~(x) + 1)) == (x)))TEE_SHMEM_START CFG_SHMEM_STARTTA_FLAG_EXEC_DDR 0typeDAIFBIT_IRQ BIT32(1)SCTLR_C BIT32(2)CHAR_MIN 0__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1TZDRAM_SIZE CFG_TZDRAM_SIZETEE_ALG_AES_CMAC 0x30000610TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZEMIDR_IMPLEMENTER_SHIFT U(24)GENMASK_32(h,l) (((~UINT32_C(0)) << (l)) & (~UINT32_C(0) >> (32 - 1 - (h))))MAX_FUNC_PRINT_SIZE 32TEE_PANIC_ID_TEE_BIGINTCONVERTFROMFMM 0x00001C02__UINT32_TYPE__ unsigned intCFG_REE_FS 1ESR_EC_SOFTSTP_EL0 U(0x32)TEE_STORAGE_PRIVATE_REE 0x80000000SPSR_MODE_RW_MASK U(0x1)TEE_TYPE_ECDSA_PUBLIC_KEY 0xA0000041__LONG_MAX__ 0x7fffffffffffffffLMIDR_IMPLEMENTER_ARM U(0x41)TCR_RES1 BIT32(31)TEE_LOGIN_TRUSTED_APP 0xF0000000ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2)CFG_CRYPTO_CCM 1__LDBL_MAX_10_EXP__ 4932TEE_INTERNAL_HASH_TO_ALGO(algo) TEE_ALG_HASH_ALGO(TEE_ALG_GET_INTERNAL_HASH(algo))CLIDR_LOC_SHIFT U(24)TA_FLAG_USER_MODE 0TEE_ATTR_CONCAT_KDF_DKM_LENGTH 0xF00003C1TAILQ_FIRST(head) ((head)->tqh_first)__ARM_FEATURE_FP16_SCALAR_ARITHMETICUINT_FAST64_MAX UINT64_MAX__ARM_ARCH_ISA_A64 1__ARM_FEATURE_AESTEE_PARAM_TYPE_MEMREF_OUTPUT 6SIZE_2G UINTPTR_C(0x80000000)UART_CR_CTSEN (1 << 15)CFG_CORE_NEX_HEAP_SIZE 16384TAILQ_FOREACH_REVERSE(var,head,headname,field) for ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last)); (var); (var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)))CFG_CORE_MAX_SYSCALL_RECURSION 4__FLT128_EPSILON__ 1.92592994438723585305597794258492732e-34F128__SIZEOF_INT128__ 16short unsigned intsigned charTEE_ATTR_PBKDF2_DKM_LENGTH 0xF00004C2UINT64_C(v) UL(v)TEE_MATTR_URX (TEE_MATTR_UR | TEE_MATTR_UX)SIMPLEQ_EMPTY(head) ((head)->sqh_first == NULL)__size_t__ INT_FAST8_MAX INT8_MAXESR_EC_AARCH32_CP14_64 U(0x0c)UART_DMACR 0x48PRIxPA_WIDTH ((int)(sizeof(paddr_t) * 2))UNISTD_H __FLT64X_HAS_INFINITY__ 1TEE_PANIC_ID_TEE_ASYMMETRICVERIFYDIGEST 0x00001104_TO_STR(x) #xCFG_NUM_THREADS 2__CHAR_BIT__ 8TEE_ALG_DES3_CBC_MAC_PKCS5 0x30000513__linux__ 1TEE_TYPE_AES 0xA0000010TEE_MEMREF_0_USED 0x00000001__ARM_FEATURE_SVE_SYS_QUEUE_H_ ROUNDUP(v,size) (((v) + ((__typeof__(v))(size) - 1)) & ~((__typeof__(v))(size) - 1))__nostackcheck __attribute__((no_instrument_function))DAIF_F_SHIFT U(6)__FLT64X_DIG__ 33__ARM_FEATURE_DOTPRODTEE_TYPE_DES3 0xA0000013CFG_TA_MBEDTLS 1_BSD_SIZE_T_ TEE_MAIN_ALGO_AES 0x10TEE_PANIC_ID_TEE_FREE 0x00000602/home/test/workspace/code/optee_3.16/optee_osTEE_MEMORY_ACCESS_ANY_OWNER 0x00000004__UINTMAX_TYPE__ long unsigned int__INT32_TYPE__ intESR_EC_DABT_EL1 U(0x25)TEE_ALG_SM4_CBC_NOPAD 0x10000114_STDDEF_H CIRCLEQ_INIT(head) do { (head)->cqh_first = (void *)(head); (head)->cqh_last = (void *)(head); } while ( 0)UART_FR_TERI (1 << 12)__noreturn __attribute__((__noreturn__))__GCC_ATOMIC_POINTER_LOCK_FREE 2TEE_ATTR_DH_PRIME 0xD0001032MPIDR_AARCH32_AFF_MASK (MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | MPIDR_AFF2_MASK)ARM64 1PRIX16 "X"_CFG_CORE_LTC_SHA384 1ROUNDDOWN(v,size) ((v) & ~((__typeof__(v))(size) - 1))__KERNEL_USER_MODE_CTX_STRUCT_H __rodata __section(".rodata" __SECTION_FLAGS_RODATA)UART_CR_UARTEN (1 << 0)TEE_OBJECT_ID_MAX_LEN 64CFG_KERN_LINKER_FORMAT elf64-littleaarch64ESR_EC_SERROR U(0x2f)__FLT32_MAX_10_EXP__ 38TEE_TIME_SUB(t1,t2,dst) do { (dst).seconds = (t1).seconds - (t2).seconds; if ((t1).millis < (t2).millis) { (dst).seconds--; (dst).millis = (t1).millis + TEE_TIME_MILLIS_BASE - (t2).millis; } else { (dst).millis = (t1).millis - (t2).millis; } } while (0)CFG_CORE_ASYNC_NOTIF_GIC_INTID 0ASSERT_H TEE_DATA_FLAG_SHARE_READ 0x00000010TEE_PANIC_ID_TEE_GETPROPERTYASBOOL 0x00000205CFG_CRYPTO_SHA512 1LL(v) v ## LLDT_STATUS_DISABLED U(0)STDINT_H vaddr_tTEE_MATTR_GLOBAL BIT(10)ID_AA64PFR1_EL1_BT_MASK ULL(0xf)TEE_ALG_RSASSA_PKCS1_V1_5_SHA384 0x70005830CFG_CRYPTO_CONCAT_KDF 1ARM32_CPSR_MODE_SYS U(0x1f)UINT16_MAX 0xffffCFG_STACK_TMP_EXTRA 0__ARM_FEATURE_SVE_VECTOR_OPERATORSCFG_ARM_GICV3 1_ANSI_STDDEF_H ULL(v) v ## ULLTEE_MAIN_ALGO_ECDH 0x42TEE_PANIC_ID_TEE_WAIT 0x00001405TEE_USAGE_VERIFY 0x00000020SPSR_32_AIF_SHIFT U(6)match_tableCFG_WARN_DECL_AFTER_STATEMENT 1TEE_CHAIN_MODE_XTS 0x4__ARM_ALIGN_MAX_STACK_PWR 16__GCC_ATOMIC_INT_LOCK_FREE 2__UINT32_C(c) c ## U__FLT64_MAX_EXP__ 1024_panic_fn(a,b,name,...) name__INT_FAST32_MAX__ 0x7fffffffffffffffLTEE_ALG_SM4_CTR 0x10000214TEE_OPERATION_AE 4__compiler_bswap32(x) __builtin_bswap32((x))__REGISTER_PREFIX__ TEE_ECC_CURVE_NIST_P384 0x00000004TEE_PANIC_ID_TEE_BIGINTCONVERTTOS32 0x00001704BIT(nr) BIT32(nr)MSG(...) trace_printf_helper(0, false, __VA_ARGS__)CIRCLEQ_INSERT_BEFORE(head,listelm,elm,field) do { QUEUEDEBUG_CIRCLEQ_HEAD((head), field) QUEUEDEBUG_CIRCLEQ_ELM((head), (listelm), field) (elm)->field.cqe_next = (listelm); (elm)->field.cqe_prev = (listelm)->field.cqe_prev; if ((listelm)->field.cqe_prev == (void *)(head)) (head)->cqh_first = (elm); else (listelm)->field.cqe_prev->field.cqe_next = (elm); (listelm)->field.cqe_prev = (elm); } while ( 0)nex_malloc(size) malloc(size)CFG_CORE_WORKAROUND_NSITR_CACHE_PRIME 1TEE_ALG_AES_GCM 0x40000810TEE_PROPSET_TEE_IMPLEMENTATION (TEE_PropSetHandle)0xFFFFFFFDCFG_WITH_VFP 1TEE_OPERATION_ASYMMETRIC_SIGNATURE 7TEE_ATTR_DH_BASE 0xD0001232TCR_EPD1 BIT32(23)TEE_MEM_INPUT 0x00000001UCHAR_MAX (SCHAR_MAX * 2 + 1)CTR_ERG_SHIFT U(20)_CFG_CORE_LTC_ACIPHER 1TEE_PANIC_ID_TEE_STARTPERSISTENTOBJECTENUMERATOR 0x00000A05IRQ_TYPE_LEVEL_LOW 8TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA512 0x70616930EMSG_RAW(...) trace_printf_helper_raw(TRACE_ERROR, true, __VA_ARGS__)TA_FLAG_REMAP_SUPPORT 0TEE_OPERATION_STATE_INITIAL 0x00000000__INT_LEAST32_MAX__ 0x7fffffffSPSR_64_MODE_EL_SHIFT U(2)__SCT_ARRAY_DEF_ITEM3(element_type,element_name,section_name) static const element_type element_name; DECLARE_KEEP_INIT(element_name); static const element_type element_name __used __section(section_name __SECTION_FLAGS_RODATA)SIMPLEQ_FIRST(head) ((head)->sqh_first)_PTRDIFF_T_ IT_UART1 40__ARM_FEATURE_BF16_SCALAR_ARITHMETICTEE_ALG_RSAES_PKCS1_V1_5 0x60000130CORTEX_A75_PART_NUM U(0xD0A)__KERNEL__ 1RAND_MAX __INT_MAX__TEE_PANIC_ID_TEE_CIPHERDOFINAL 0x00000E01UART_LCRH_SPS (1 << 7)MPIDR_MT_SHIFT U(24)__STDC_HOSTED__ 1TEE_ERROR_CANCEL 0xFFFF0002TEE_ATTR_PBKDF2_ITERATION_COUNT 0xF00003C2TEE_LOGIN_APPLICATION_GROUP 0x00000006TEE_PARAM_TYPE_VALUE_INOUT 3TEE_TYPE_DH_KEYPAIR 0xA1000032CFG_CRYPTO_SHA384 1CFG_WITH_SOFTWARE_PRNG 1__FLT32_MAX_EXP__ 128__LDBL_MIN_10_EXP__ (-4931)TEE_ALG_GET_DIGEST_SIZE(algo) __tee_alg_get_digest_size(algo)PRIo8 "o"SIMPLEQ_ENTRY(type) struct { struct type *sqe_next; }__ARM_64BIT_STATE 1TEE_TYPE_HMAC_SHA224 0xA0000003CTR_IMINLINE_SHIFT U(0)__FLT_DENORM_MIN__ 1.40129846432481707092372958328991613e-45FTLBI_ASID_SHIFT U(48)__DBL_HAS_DENORM__ 1INT_LEAST16_MIN INT16_MIN__UINT32_MAX__ 0xffffffffU__FLT64_MAX_10_EXP__ 308__FLT16_DECIMAL_DIG__ 5TEE_PANIC_ID_TEE_GETPROPERTYASBINARYBLOCK 0x00000204SHIFT_U64(v,shift) ((uint64_t)(v) << (shift))STAILQ_ENTRY(type) struct { struct type *stqe_next; }__STDC__ 1MAX_UNSAFE(a,b) (((a) > (b)) ? (a) : (b))TEE_ATTR_RSA_PRIME2 0xC0000530TEE_PANIC_ID_TEE_MALLOC 0x00000604UART_CR 0x30__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A)TEE_ATTR_CONCAT_KDF_OTHER_INFO 0xD00002C1phys_sdp_mem_end SCATTERED_ARRAY_END(phys_sdp_mem, struct core_mmu_phys_mem)TEE_PANIC_ID_TEE_BIGINTNEG 0x00001904__GNUC_STDC_INLINE__ 1UART_LCRH_WLEN_6 (1 << 5)PRIi32 "i"USER_TA_HEADER_H __FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32x_CFG_CORE_LTC_SHA512 1__ARM_FPCIRCLEQ_FOREACH(var,head,field) for ((var) = ((head)->cqh_first); (var) != (const void *)(head); (var) = ((var)->field.cqe_next))TEE_ALG_HMAC_SHA1 0x30000002TEE_ALG_HKDF_SHA384_DERIVE_KEY 0x800050C0CFG_TZDRAM_START 0x0e100000TEE_PANIC_ID_TEE_STARTPROPERTYENUMERATOR 0x0000020CTEE_PANIC_ID_TEE_RESETPERSISTENTOBJECTENUMERATOR 0x00000A04__WCHAR_WIDTH__ 32TEE_PANIC_ID_TEE_BIGINTMULMOD 0x00001A04MM_PGT_CACHE_H TEE_MATTR_SECURE BIT(11)__FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64TEE_PANIC_ID_TEE_ASYMMETRICDECRYPT 0x00001101TEE_MAIN_ALGO_DES2 0x12TEE_MM_H __PTRDIFF_T TRACE_ERROR 1TEE_ALG_SM2_PKE 0x80000045__attr_const __attribute__((__const__))INT64_C(v) L(v)IS_ALIGNED(x,a) (((x) & ((a) - 1)) == 0)PRIu64 __PRI64_PREFIX "u"__ARM_FEATURE_CRYPTOTEE_STORAGE_PRIVATE_SQL_RESERVED 0x80000200INT_FAST16_MAX INT16_MAXTAILQ_INSERT_HEAD(head,elm,field) do { QUEUEDEBUG_TAILQ_INSERT_HEAD((head), (elm), field) if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) (head)->tqh_first->field.tqe_prev = &(elm)->field.tqe_next; else (head)->tqh_last = &(elm)->field.tqe_next; (head)->tqh_first = (elm); (elm)->field.tqe_prev = &(head)->tqh_first; } while ( 0)register_phys_mem(type,addr,size) __register_memory(#addr, (type), (addr), (size), phys_mem_map)__FLT32_HAS_DENORM__ 1DAIF_A BIT32(8)TEE_U16_TO_BIG_ENDIAN(x) TEE_U16_BSWAP(x)TEE_TYPE_HMAC_SM3 0xA0000007UART1_BASE 0x09040000SLIST_EMPTY(head) ((head)->slh_first == NULL)TEE_ALG_RSAES_PKCS1_OAEP_MGF1_SHA384 0x60510230CORE_MMU_USER_PARAM_MASK ((paddr_t)CORE_MMU_USER_PARAM_SIZE - 1)STAILQ_INSERT_TAIL(head,elm,field) do { (elm)->field.stqe_next = NULL; *(head)->stqh_last = (elm); (head)->stqh_last = &(elm)->field.stqe_next; } while ( 0)TEE_PANIC_ID_TEE_MEMCOMPARE 0x00000605TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA224 0x70313930__LDBL_MAX__ 1.18973149535723176508575932662800702e+4932LTEE_PARAM_TYPE_GET(t,i) ((((uint32_t)t) >> ((i)*4)) & 0xF)TEE_ALG_HMAC_ALGO(main_hash) (TEE_OPERATION_MAC << 28 | (main_hash))CORTEX_A7_PART_NUM U(0xC07)TEE_CHAIN_MODE_PKCS1_PSS_MGF1 0x9uint32_tTEE_TYPE_PBKDF2_PASSWORD 0xA10000C2__SIZE_T __FLT_MIN_EXP__ (-125)__SHRT_WIDTH__ 16CORTEX_A15_PART_NUM U(0xC0F)STAILQ_REMOVE_HEAD(head,field) do { if (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) (head)->stqh_last = &(head)->stqh_first; } while ( 0)__GCC_ATOMIC_SHORT_LOCK_FREE 2TEE_PANIC_ID_TEE_ALLOCATETRANSIENTOBJECT 0x00000801TEE_SHMEM_SIZE CFG_SHMEM_SIZECIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev)TEE_CHAIN_MODE_ECB_NOPAD 0x0CFG_CORE_HEAP_SIZE 65536uintptr_t__VERSION__ "10.2.1 20201103"PAR_PA_SHIFT U(12)__GCC_ASM_FLAG_OUTPUTS__ 1__SIZEOF_POINTER__ 8TEE_PANIC_ID_TEE_RESTRICTOBJECTUSAGE1 0x00000707ESR_EC_SHIFT U(26)__FLT128_NORM_MAX__ 1.18973149535723176508575932662800702e+4932F128__ARM_FEATURE_SHA2__ARM_FEATURE_SHA3TA_PROP_STR_DESCRIPTION "gpd.ta.description"_T_SIZE TEE_ATTR_ECC_EPHEMERAL_PUBLIC_VALUE_X 0xD0000946TEE_PANIC_ID_TEE_MACINIT 0x00000F03TEE_ATTR_SM2_KEP_CONFIRMATION_IN 0xD0000746PRIu16 "u"UTEE_SE_READER_TEE_ONLY (1 << 1)TEE_ALG_GET_CLASS(algo) __tee_alg_get_class(algo)TEE_MM_POOL_HI_ALLOC (1u << 0)__printf(a,b) __attribute__((format(printf, a, b)))__panic(str) __do_panic(__FILE__, __LINE__, __func__, str)pl011_opsMPIDR_AFF2_SHIFT U(16)TEE_ALG_RSASSA_PKCS1_V1_5_SHA256 0x70004830PRIo64 __PRI64_PREFIX "o"long unsigned intCFG_CORE_RESERVED_SHM 1__compiler_atomic_store(p,val) __atomic_store_n((p), (val), __ATOMIC_RELAXED)TEE_DATA_MAX_POSITION 0xFFFFFFFF__LONG_LONG_MAX__ 0x7fffffffffffffffLLTHREAD_CORE_LOCAL_ALIGNED __aligned(16)CFG_MMAP_REGIONS 13TEE_ALG_RSAES_PKCS1_OAEP_MGF1_SHA256 0x60410230QUEUEDEBUG_TAILQ_PREREMOVE(head,elm,field) TEE_ALG_SHA512 0x50000006TEE_PANIC_ID_TEE_GETOBJECTINFO1 0x00000706__UINT_LEAST64_MAX__ 0xffffffffffffffffUL__STDC_VERSION__ 199901LKERNEL_MUTEX_H __ARM_FEATURE_BTI_DEFAULTTCR_EL1_IPS_MASK UINT64_C(0x7)__UINT16_C(c) cpanic(...) _panic_fn("", ##__VA_ARGS__, _panic1, _panic0)(__VA_ARGS__)EMSG(...) trace_printf_helper(TRACE_ERROR, true, __VA_ARGS__)TEE_CHAIN_MODE_CTS 0x3TEE_PANIC_ID_TEE_MACUPDATE 0x00000F04DT_INFO_INVALID_CLOCK -1__always_inline __attribute__((always_inline)) inline__UINT8_TYPE__ unsigned char__UINTPTR_MAX__ 0xffffffffffffffffULTRACE_H PLATFORM_CONFIG_H __GCC_ATOMIC_LLONG_LOCK_FREE 2UART_FR_RXFE (1 << 4)TRACE_DEBUG 3CFG_HWSUPP_MEM_PERM_PXN 1TEE_TYPE_CORRUPTED_OBJECT 0xA00000BEQUEUEDEBUG_LIST_INSERT_HEAD(head,elm,field) TEE_ATTR_HKDF_OKM_LENGTH 0xF00004C0TEE_MATTR_PROT_MASK (TEE_MATTR_PRWX | TEE_MATTR_URWX | TEE_MATTR_GUARDED)__LONG_LONG_WIDTH__ 64TEE_ECC_CURVE_SM2 0x00000300TEE_MAC_SIZE_AES_CBC_MAC_PKCS5 __SCT_ARRAY_DEF_PG_ITEM3(element_type,element_name,section_name) static const element_type element_name __used __section(section_name __SECTION_FLAGS_RODATA)SCTLR_SA BIT32(3)TEE_SDP_TEST_MEM_SIZE 0charADD_OVERFLOW(a,b,res) __compiler_add_overflow((a), (b), (res))CFG_PKCS11_TA_HEAP_SIZE (32 * 1024)TEE_PANIC_ID_TEE_FREETRANSIENTOBJECT 0x00000803_CFG_CORE_LTC_SIZE_OPTIMIZATION 1TEE_ATTR_SM2_ID_INITIATOR 0xD0000446SIZE_1M UINTPTR_C(0x100000)TEE_PANIC_ID_TEE_DERIVEKEY 0x00001201TEE_ECC_CURVE_NIST_P224 0x00000002TEE_LOGIN_APPLICATION 0x00000004FILE_TAG_SIZE TEE_SHA256_HASH_SIZE_CFG_CORE_LTC_RSA 1CFG_TEE_FW_IMPL_VERSION FW_IMPL_UNDEF__UINT_LEAST16_TYPE__ short unsigned intfallthrough __attribute__((__fallthrough__))ESR_EC_AARCH32_CP14_LS U(0x06)__LDBL_HAS_QUIET_NAN__ 1__ARM_FEATURE_SHA512CFG_TA_ASLR_MIN_OFFSET_PAGES 0TEE_MATTR_PX BIT(6)__WCHAR_MAX__ 0xffffffffU__FLT64_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F64_SIZE_T UART_FR 0x18TEE_PANIC_ID_TEE_ALLOCATEPROPERTYENUMERATOR 0x00000201TA_FLAGS_MASK GENMASK_32(10, 0)__ARM_NEONPRIi8 "i"FMSG_RAW(...) (void)0CFG_CRYPTO_HMAC 1TEE_PANIC_ID_TEE_BIGINTSUBMOD 0x00001A06__nex_data THREAD_RPC_MAX_NUM_PARAMS U(4)CORE_MMU_BASE_TABLE_SHIFT U(30)__FLT64X_MANT_DIG__ 113IO_H true 1ESR_FSC_ALIGN U(0x21)__compiler_bswap64(x) __builtin_bswap64((x))__FLT16_DENORM_MIN__ 5.96046447753906250000000000000000000e-8F16ESR_EC_SP_ALIGN U(0x26)TEE_TYPE_HMAC_MD5 0xA0000001CORE_MMU_PGDIR_SHIFT U(21)TEE_ALG_AES_CBC_NOPAD 0x10000110_SIZE_T_DEFINED QUEUEDEBUG_TAILQ_POSTREMOVE(elm,field) __FLT128_MAX__ 1.18973149535723176508575932662800702e+4932F128__DECLARE_KEEP_PAGER1(sym,file_id) __DECLARE_KEEP_PAGER2(sym, file_id)CFG_TA_ASLR_MAX_OFFSET_PAGES 128UART_LCRH_WLEN_5 (0 << 5)ARM32_CPSR_MODE_SVC U(0x13)__SIG_ATOMIC_WIDTH__ 32HW_UNIQUE_KEY_LENGTH (16)TEE_ERROR_NO_DATA 0xFFFF000B__bool_true_false_are_defined 1io_pa_or_vaTEE_ATTR_SM2_KEP_CONFIRMATION_OUT 0xD0000846__INT_FAST64_TYPE__ long intCORTEX_A72_PART_NUM U(0xD08)ESR_FSC_ACCF_L1 U(0x09)ESR_EC_FP_ASIMD U(0x07)SPSR_32_E_BIG U(0x1)CFG_PKCS11_TA_AUTH_TEE_IDENTITY 1TEE_PANIC_ID_TEE_BIGINTSQUARE 0x00001905CFG_CRYPTO_SHA512_256 1THREAD_EXCP_FOREIGN_INTR (ARM32_CPSR_F >> ARM32_CPSR_F_SHIFT)CIRCLEQ_HEAD(name,type) struct name { struct type *cqh_first; struct type *cqh_last; }SPSR_64_MODE_SP_MASK U(0x1)CONSOLE_UART_BASE UART1_BASENULL ((void *)0)TEE_PANIC_ID_TEE_BIGINTINVMOD 0x00001A02TEE_PROPSET_CURRENT_TA (TEE_PropSetHandle)0xFFFFFFFFUART0_BASE 0x09000000__ORDER_BIG_ENDIAN__ 4321CFG_TEE_CORE_DEBUG 1CFG_CRYPTO_GCM 1__gnu_linux__ 1INT_FAST8_MIN INT8_MINUART_CR_DTR (1 << 10)CFG_CRYPTO_RSA 1THREAD_ID_0 0__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1__FLT64X_HAS_DENORM__ 1__FLT64_MIN_EXP__ (-1021)__KERNEL_REFCOUNT_H _CFG_CORE_LTC_MD5 1_panic1(s) __panic(s)TEE_PANIC_ID_TEE_CIPHERUPDATE 0x00000E03tee_pbuf_is core_pbuf_isdev_initCFG_COMPAT_GP10_DES 1__INTPTR_WIDTH__ 64io_write32OUTRMSG(r) do { OUTMSG("r=[%x]", r); return r; } while (0)ESR_FSC_TRANS_L1 U(0x05)CFG_GP_SOCKETS 1TRACE_PRINTF_LEVEL TRACE_ERRORESR_FSC_TRANS_L0 U(0x04)__FLT32X_MAX__ 1.79769313486231570814527423731704357e+308F32xTEE_MAIN_ALGO_DH 0x32__compiler_add_overflow(a,b,res) __builtin_add_overflow((a), (b), (res))__need_wchar_t__FLT_DECIMAL_DIG__ 9pl011_initTEE_MM_POOL_NEX_MALLOC (1u << 1)_T_PTRDIFF TEE_OPERATION_MAC 3TEE_TYPE_HMAC_SHA512 0xA0000006UINT_LEAST32_MAX UINT32_MAXCIRCLEQ_ENTRY(type) struct { struct type *cqe_next; struct type *cqe_prev; }TEE_PANIC_ID_TEE_PANIC 0x00000301INT_LEAST8_MIN INT8_MIN__FLT64X_EPSILON__ 1.92592994438723585305597794258492732e-34F64x_CFG_CORE_LTC_SHA384_DESC 1CTR_ERG_MASK U(0xf)chip_to_baseSYS_CDEFS_H __FLT128_MAX_EXP__ 16384__GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)CFG_TEE_CORE_LOG_LEVEL 3MIDR_IMPLEMENTER_WIDTH U(8)__linux 1UINT32_MAX 0xffffffffUsizeTEE_CHAIN_MODE_CBC_NOPAD 0x1SLIST_INSERT_AFTER(slistelm,elm,field) do { (elm)->field.sle_next = (slistelm)->field.sle_next; (slistelm)->field.sle_next = (elm); } while ( 0)__FLT128_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F128__WINT_MIN__ 0UCFG_PKCS11_TA_TOKEN_COUNT 3__FINITE_MATH_ONLY__ 0__noinline __attribute__((noinline))__pie__ 1driver__ARM_FEATURE_BF16_VECTOR_ARITHMETICCORTEX_A17_PART_NUM U(0xC0E)CFG_LOCKDEP_RECORD_STACK 1TEE_ATTR_RSA_PRIME1 0xC0000430SPSR_32_MODE_USR U(0x0)DAIF_AIF (DAIF_A | DAIF_I | DAIF_F)UART_LCRH_FEN (1 << 4)__INT_LEAST64_MAX__ 0x7fffffffffffffffLTEE_PANIC_ID_TEE_RESETPROPERTYENUMERATOR 0x0000020BKERN_IDENTITY ((TEE_Identity *)-1)DEFINE_REG_READ_FUNC_(reg,type,asmreg) static inline __noprof type read_ ##reg(void) { uint64_t val64 = 0; asm volatile("mrs %0, " #asmreg : "=r" (val64)); return val64; }CFG_SECURE_TIME_SOURCE_CNTPCT 1TEE_PANIC_ID_TEE_BIGINTCMPS32 0x00001802__ARM_BIG_ENDIANTEE_PANIC_ID_TEE_BIGINTADDMOD 0x00001A01__ARM_SIZEOF_MINIMAL_ENUM 4read_midr() read_midr_el1()CFG_CORE_RWDATA_NOEXEC 1CORE_MMU_USER_PARAM_SHIFT SMALL_PAGE_SHIFTSPSR_32_T_THUMB U(0x1)TEE_ALG_ECDSA_P256 0x70003041CTR_WORD_SIZE U(4)CFG_CRYPTO_MD5 1GICD_OFFSET 0TEE_MAIN_ALGO_HKDF 0xC0TEE_PANIC_ID_TA_CLOSESESSIONENTRYPOINT 0x00000101_CFG_CORE_LTC_HMAC 1__FLT64_DIG__ 15GNU C99 10.2.1 20201103 -mstrict-align -mno-outline-atomics -mgeneral-regs-only -mlittle-endian -mabi=lp64 -g3 -Os -std=gnu99 -ffunction-sections -fdata-sections -fpie__GCC_ATOMIC_BOOL_LOCK_FREE 2TEE_CHAIN_MODE_CBC_MAC_PKCS5 0x5ESR_EC_PC_ALIGN U(0x22)register_phys_mem_ul(type,addr,size) __register_memory_ul(#addr, (type), (addr), (size), phys_mem_map)compatibleARM64_H TEE_ERROR_STORAGE_NOT_AVAILABLE 0xF0100003CIRCLEQ_INSERT_TAIL(head,elm,field) do { QUEUEDEBUG_CIRCLEQ_HEAD((head), field) (elm)->field.cqe_next = (void *)(head); (elm)->field.cqe_prev = (head)->cqh_last; if ((head)->cqh_first == (void *)(head)) (head)->cqh_first = (elm); else (head)->cqh_last->field.cqe_next = (elm); (head)->cqh_last = (elm); } while ( 0)CIRCLEQ_INSERT_AFTER(head,listelm,elm,field) do { QUEUEDEBUG_CIRCLEQ_HEAD((head), field) QUEUEDEBUG_CIRCLEQ_ELM((head), (listelm), field) (elm)->field.cqe_next = (listelm)->field.cqe_next; (elm)->field.cqe_prev = (listelm); if ((listelm)->field.cqe_next == (void *)(head)) (head)->cqh_last = (elm); else (listelm)->field.cqe_next->field.cqe_prev = (elm); (listelm)->field.cqe_next = (elm); } while ( 0)__DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L)INT8_MAX 0x7fESR_FSC_TRANS_L3 U(0x07)SIZE_4M UINTPTR_C(0x400000)SIZE_MAX ULONG_MAXPRIxPASZ PRIxPTR_CFG_CORE_LTC_AES 1_STDINT_H __SCT_ARRAY_DEF_ITEM2(array_name,order,id,element_type) __SCT_ARRAY_DEF_ITEM3(element_type, __scattered_array_ ## id ## array_name, ".scattered_array_" #array_name "_1_" #order)TEE_ALG_GET_MAIN_ALG(algo) __tee_alg_get_main_alg(algo)ESR_EC_AARCH32_CP10_ID U(0x08)TCR_T0SZ_SHIFT U(0)TEE_PANIC_ID_TEE_GETOPERATIONINFO 0x00000C04TEE_ALG_ECDH_P256 0x80003042__FLT16_HAS_INFINITY__ 1CFG_DEVICE_ENUM_PTA 1TEE_TYPE_CONCAT_KDF_Z 0xA10000C1tee_pbuf_is_non_sec(buf,len) core_pbuf_is(CORE_MEM_NON_SEC, (paddr_t)(buf), (len))__ARM_PCS_AAPCS64 1__FLT64X_DECIMAL_DIG__ 36TEE_ATTR_ECC_CURVE 0xF0000441UTEE_SE_READER_PRESENT (1 << 0)TEE_MATTR_CACHE_MASK U(0x7)TEE_PANIC_ID_TEE_BIGINTFMMSIZEINU32 0x00001502__ARM_SIZEOF_WCHAR_T 4ARM32_CPSR_MODE_USR U(0x10)__SIZEOF_DOUBLE__ 8STAILQ_REMOVE_AFTER(head,elm,field) do { if ((STAILQ_NEXT(elm, field) = STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) (head)->stqh_last = &STAILQ_NEXT((elm), field); } while (0)TEE_ALG_CONCAT_KDF_SHA224_DERIVE_KEY 0x800030C1INTMAX_MIN INT64_MINLIST_FIRST(head) ((head)->lh_first)__FLT32_MIN__ 1.17549435082228750796873653722224568e-38F32_BSD_WCHAR_T_ __ARM_FEATURE_FP16_VECTOR_ARITHMETICCFG_PKCS11_TA_ALLOW_DIGEST_KEY 1_CFG_CORE_LTC_OPTEE_THREAD 1CFG_CRYPTO_SM3 1TEE_MATTR_PR BIT(4)TEE_U32_TO_BIG_ENDIAN(x) TEE_U32_BSWAP(x)LIST_EMPTY(head) ((head)->lh_first == NULL)__compiler_sub_overflow(a,b,res) __builtin_sub_overflow((a), (b), (res))__LDBL_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966LTEE_PANIC_ID_TEE_CLOSETASESSION 0x00000401TEE_PANIC_ID_TEE_GETOBJECTINFO 0x00000703UTEE_SE_READER_SELECT_RESPONE_ENABLE (1 << 2)U(v) v ## U_CFG_CORE_LTC_XTS 1TEE_ATTR_RSA_PRIVATE_EXPONENT 0xC0000330TCR_XRGNX_WBWA U(0x3)CFG_CORE_THREAD_SHIFT 0__FLT64_NORM_MAX__ 1.79769313486231570814527423731704357e+308F64TEE_MATTR_URWX (TEE_MATTR_URW | TEE_MATTR_UX)READ_ONCE(p) __compiler_atomic_load(&(p))TEE_TIME_LE(t1,t2) (((t1).seconds == (t2).seconds) ? ((t1).millis <= (t2).millis) : ((t1).seconds <= (t2).seconds))TA_FLAG_SINGLE_INSTANCE (1 << 2)MPIDR_AFF2_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)TEE_PANIC_ID_TEE_INITVALUEATTRIBUTE 0x00000806__OPTIMIZE__ 1TCR_TG1_4KB SHIFT_U32(2, 30)TEE_USAGE_ENCRYPT 0x00000002_CFG_CORE_LTC_SM2_DSA 1CFG_CRYPTO_CBC_MAC 1__PRI64_PREFIX "l"_CFG_CORE_LTC_SM2_KEP 1CFG_OS_REV_REPORTS_GIT_SHA1 1__AARCH64_CMODEL_SMALL__serial_opsSUB_OVERFLOW(a,b,res) __compiler_sub_overflow((a), (b), (res))TEE_TYPE_HKDF_IKM 0xA10000C0TEE_ALG_HMAC_SM3 0x30000007LIST_REMOVE(elm,field) do { QUEUEDEBUG_LIST_OP((elm), field) if ((elm)->field.le_next != NULL) (elm)->field.le_next->field.le_prev = (elm)->field.le_prev; *(elm)->field.le_prev = (elm)->field.le_next; QUEUEDEBUG_LIST_POSTREMOVE((elm), field) } while ( 0)__OPTIMIZE_SIZE__ 1SPSR_64_MODE_SP_SHIFT U(0)__weak __attribute__((weak))__FLT16_DIG__ 3STAILQ_FOREACH_SAFE(var,head,field,tvar) for ((var) = STAILQ_FIRST((head)); (var) && ((tvar) = STAILQ_NEXT((var), field), 1); (var) = (tvar))CFG_STACK_THREAD_EXTRA 0TAILQ_REMOVE(head,elm,field) do { QUEUEDEBUG_TAILQ_PREREMOVE((head), (elm), field) QUEUEDEBUG_TAILQ_OP((elm), field) if (((elm)->field.tqe_next) != NULL) (elm)->field.tqe_next->field.tqe_prev = (elm)->field.tqe_prev; else (head)->tqh_last = (elm)->field.tqe_prev; *(elm)->field.tqe_prev = (elm)->field.tqe_next; QUEUEDEBUG_TAILQ_POSTREMOVE((elm), field); } while ( 0)TA_FLAG_CACHE_MAINTENANCE (1 << 7)CFG_CRYPTO_HKDF 1__pure __attribute__((pure))__ATOMIC_ACQ_REL 4LIST_FOREACH_SAFE(var,head,field,tvar) for ((var) = LIST_FIRST((head)); (var) && ((tvar) = LIST_NEXT((var), field), 1); (var) = (tvar))_T_WCHAR _SIZET_ __INT8_TYPE__ signed charTEE_CHAIN_MODE_CTR 0x2TEE_ATTR_HKDF_INFO 0xD00003C0ESR_EC_UNKNOWN U(0x00)SPSR_64_DAIF_SHIFT U(6)__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1IRQ_TYPE_LEVEL_HIGH 4THREAD_EXCP_NATIVE_INTR (ARM32_CPSR_I >> ARM32_CPSR_F_SHIFT)ARM32_CPSR_IT_MASK1 U(0x06000000)__register_memory(_name,_type,_addr,_size,_section) SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = { .name = (_name), .type = (_type), .addr = (_addr), .size = (_size) }chip_STDDEF_H_ PRIu32 "u"THREAD_PARAM_MEMREF(_direction,_mobj,_offs,_size) (struct thread_param){ .attr = THREAD_PARAM_ATTR_MEMREF_ ## _direction, .u.memref = { .mobj = (_mobj), .offs = (_offs), .size = (_size) } }TEE_ERROR_TIME_NOT_SET 0xFFFF5000TEE_API_TYPES_H tee_vbuf_is_sec(buf,len) core_vbuf_is(CORE_MEM_SEC, (void *)(buf), (len))TEE_ALG_CONCAT_KDF_SHA512_DERIVE_KEY 0x800060C1PAR_F BIT32(0)ARM32_CPSR_MODE_MON U(0x16)TAILQ_FOREACH(var,head,field) for ((var) = ((head)->tqh_first); (var); (var) = ((var)->field.tqe_next))vbase__ARM_FEATURE_UNALIGNED 1__ARM_FEATURE_SVE2_BITPERMTRACE_MAX TRACE_FLOW_CONCAT(x,y) x ##yTEE_PANIC_ID_TA_INVOKECOMMANDENTRYPOINT 0x00000104TEE_TYPE_DSA_KEYPAIR 0xA1000031__INT8_C(c) cINMSG(...) FMSG("> " __VA_ARGS__)__INT_FAST8_TYPE__ signed charTHREAD_PARAM_VALUE(_direction,_a,_b,_c) (struct thread_param){ .attr = THREAD_PARAM_ATTR_VALUE_ ## _direction, .u.value = { .a = (_a), .b = (_b), .c = (_c) } }CFG_CRYPTO_XTS 1TCR_A1 BIT32(22)_CFG_FTRACE_BUF_WHEN_FULL_shift 1TEE_TYPE_RSA_PUBLIC_KEY 0xA0000030TLBI_ASID_MASK U(0xff)TEE_AES_BLOCK_SIZE 16ULTEE_PANIC_ID_TEE_BIGINTMUL 0x00001903__FLT32X_MIN_EXP__ (-1021)TEE_ALG_RSASSA_PKCS1_V1_5_SHA224 0x70003830TEE_ERROR_ACCESS_CONFLICT 0xFFFF0003LIMITS_H ESR_EC_MASK U(0x3f)_BSD_PTRDIFF_T_ __WCHAR_T __DBL_DIG__ 15TEE_ALG_DES3_CBC_NOPAD 0x10000113TEE_ALG_RSASSA_PKCS1_V1_5_SHA512 0x70006830CFG_IN_TREE_EARLY_TAS trusted_keys/f04a0fe7-1f5d-4b9b-abf7-619b85b4ce8cfor_each_dt_driver(drv) for (drv = SCATTERED_ARRAY_BEGIN(dt_drivers, struct dt_driver); drv < SCATTERED_ARRAY_END(dt_drivers, struct dt_driver); drv++)VM_FLAG_SHAREABLE BIT(2)TEE_MAIN_ALGO_DSA 0x31SPSR_32_MODE_SHIFT U(0)TEE_PANIC_ID_TEE_BIGINTCOMPUTEEXTENDEDGCD 0x00001B01CIRCLEQ_HEAD_INITIALIZER(head) { (void *)&head, (void *)&head }__INT64_TYPE__ long intSTAILQ_HEAD(name,type) struct name { struct type *stqh_first; struct type **stqh_last; }DAIFBIT_FIQ BIT32(0)TEE_PANIC_ID_TEE_WRITEOBJECTDATA 0x00000B04DEFINE_U64_REG_READWRITE_FUNCS(reg) DEFINE_U64_REG_READ_FUNC(reg) DEFINE_U64_REG_WRITE_FUNC(reg)__INT16_C(c) cMPIDR_AFF1_SHIFT U(8)TEE_ERROR_EXTERNAL_CANCEL 0xFFFF0011TEE_PANIC_ID_TEE_BIGINTCMP 0x00001801__INT_FAST8_MAX__ 0x7fTEE_MALLOC_FILL_ZERO 0x00000000__unix__ 1MUL_OVERFLOW(a,b,res) __compiler_mul_overflow((a), (b), (res))__FLT128_HAS_INFINITY__ 1TEE_MEMORY_ACCESS_SECURE 0x20000000__unused __attribute__((unused))_VA_LIST_ TEE_CHAIN_MODE_CMAC 0x6L(v) v ## L__UINT_FAST16_TYPE__ long unsigned intUINT_LEAST8_MAX UINT8_MAXMIDR_PRIMARY_PART_NUM_WIDTH U(12)TEE_PANIC_ID_TEE_GETINSTANCEDATA 0x00000603TEE_TYPE_ECDH_KEYPAIR 0xA1000042__UINT8_MAX__ 0xffCHAR_MAX UCHAR_MAXTEE_ALG_RSASSA_PKCS1_V1_5_SHA1 0x70002830TEE_PANIC_ID_TEE_SETINSTANCEDATA 0x00000609__compiler_bswap16(x) __builtin_bswap16((x))CFG_CRYPTO_CBC_MAC_BUNDLE_BLOCKS 64TEE_ERROR_ITEM_NOT_FOUND 0xFFFF0008CORE_MMU_H CFG_CC_OPT_LEVEL sTEE_MATTR_UR BIT(7)TEE_PANIC_ID_TEE_BIGINTFMMCONTEXTSIZEINU32 0x00001501CFG_TEE_CORE_EMBED_INTERNAL_TESTS 1__UINT_FAST8_MAX__ 0xff__FLT64_EPSILON__ 2.22044604925031308084726333618164062e-16F64__SIZEOF_WINT_T__ 4CFG_TEE_FW_MANUFACTURER FW_MAN_UNDEFTEE_PANIC_ID_TEE_MACCOMPUTEFINAL 0x00000F02__FLT64_DECIMAL_DIG__ 17TEE_PANIC_ID_TEE_BIGINTINIT 0x00001601TEE_ALG_ECDSA_P192 0x70001041pl011_match_table_VA_LIST PRIxPA PRIxPTRCFG_LIBUTILS_WITH_ISOC 1TRACE_MIN 0paddr_tARM32_CPSR_T BIT(5)__FLT32_EPSILON__ 1.19209289550781250000000000000000000e-7F32ESR_FSC_SIZE_L0 U(0x00)__ATOMIC_CONSUME 1__INT_LEAST16_TYPE__ short int__ARM_FEATURE_FRINTESR_EC_AARCH32_SVC U(0x11)SPSR_64_MODE_EL_MASK U(0x3)CFG_CORE_HUK_SUBKEY_COMPAT 1pl011_driverCFG_GIC 1UDIV_ROUND_NEAREST(x,y) (__extension__ ({ __typeof__(x) _x = (x); __typeof__(y) _y = (y); (_x + (_y / 2)) / _y; }))TEE_DATA_FLAG_SHARE_WRITE 0x00000020TEE_MAIN_ALGO_PBKDF2 0xC2__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2CFG_HWSUPP_MEM_PERM_WXN 1__INT_LEAST32_TYPE__ intTEE_PANIC_ID_TEE_BIGINTGETBIT 0x00001803__SIZEOF_PTRDIFF_T__ 8TEE_TYPE_SM2_DSA_KEYPAIR 0xA1000045nex_free(ptr) free(ptr)TEE_TIME_LT(t1,t2) (((t1).seconds == (t2).seconds) ? ((t1).millis < (t2).millis) : ((t1).seconds < (t2).seconds))CFG_SHMEM_SIZE 0x00200000TEE_ALG_DES_CBC_NOPAD 0x10000111TEE_TYPE_DSA_PUBLIC_KEY 0xA0000031INT64_MIN (-0x7fffffffffffffffL-1)__ARM_FEATURE_COMPLEXUART_FR_DCD (1 << 2)virt_to_phys_VA_LIST_T_H TEE_ALG_ECDH_P192 0x80001042__FLT32X_HAS_QUIET_NAN__ 1MPIDR_CPU_MASK MPIDR_AFF0_MASKTEE_PANIC_ID_TEE_MEMMOVE 0x00000607TEE_ALG_RSAES_PKCS1_OAEP_MGF1_SHA1 0x60210230SPSR_32_MODE_MASK U(0xf)CPACR_EL1_FPEN_MASK U(0x3)TA_FLAG_DEVICE_ENUM_SUPP (1 << 10)ESR_FSC_SIZE_L1 U(0x01)__DBL_MIN_EXP__ (-1021)__FLT64X_MIN_EXP__ (-16381)TYPES_EXT_H CFG_CRYPTO_SM4 1UART_CR_OUT1 (1 << 12)TEE_PANIC_ID_TEE_BIGINTCONVERTTOOCTETSTRING 0x00001703TEE_ALG_DSA_SHA224 0x70003131TEE_ERROR_SHORT_BUFFER 0xFFFF0010TEE_MAIN_ALGO_DES3 0x13pl011_have_rx_dataCOMPILE_TIME_ASSERT(x) do { switch (0) { case 0: case ((x) ? 1: 0): default : break; } } while (0)DT_INFO_INVALID_REG_SIZE ((size_t)-1)mdbg_check(x) do { } while (0)nameIRQ_TYPE_EDGE_FALLING 2DIV_ROUND_UP(x,y) (((x) + (y) - 1) / (y))UART_FR_TXFE (1 << 7)PRId16 "d"TEE_PANIC_ID_TEE_BIGINTGETBITCOUNT 0x00001804ESR_FSC_MASK U(0x3f)__ARM_FEATURE_CRC32TEE_U64_FROM_BIG_ENDIAN(x) TEE_U64_BSWAP(x)TEE_SE_READER_NAME_MAX 20CFG_CRYPTO_CMAC 1TEE_U64_BSWAP(x) __compiler_bswap64((x))TEE_PANIC_ID_TEE_AEINIT 0x00001003bool _Bool___int_ptrdiff_t_h KERNEL_DT_H CTR_DMINLINE_MASK (BIT(4) - 1)__FLT128_HAS_QUIET_NAN__ 1TEE_MAIN_ALGO_SHA224 0x03TEE_USAGE_DERIVE 0x00000040TEE_ATTR_RSA_MODULUS 0xD0000130TEE_PARAM_TYPE_SET(t,i) (((uint32_t)(t) & 0xF) << ((i)*4))SCTLR_M BIT32(0)TCR_XRGNX_NC U(0x0)__used __attribute__((__used__))CFG_REE_FS_TA 1TEE_ALG_SHA256 0x50000004register_sdp_mem(addr,size) static int CONCAT(__register_sdp_mem_unused, __COUNTER__) __unusedESR_EC_AARCH64_BRK U(0x3c)TEE_ALG_HKDF_MD5_DERIVE_KEY 0x800010C0PL011_H TEE_TYPE_SM2_PKE_KEYPAIR 0xA1000047CFG_EMBEDDED_TS 1CFG_WITH_ARM_TRUSTED_FW 1__FLT32X_HAS_DENORM__ 1DECLARE_KEEP_INIT(sym) __DECLARE_KEEP_INIT1(sym, __FILE_ID__)io_pa_va__FLT32_HAS_QUIET_NAN__ 1ESR_FSC_PERMF_L1 U(0x0d)MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1)PRIi16 "i"__LDBL_NORM_MAX__ 1.18973149535723176508575932662800702e+4932LTA_PROP_STR_DATA_SIZE "gpd.ta.dataSize"CFG_CORE_MBEDTLS_MPI 1TEE_ALG_SHA1 0x50000002ARM_H CIRCLEQ_LOOP_PREV(head,elm,field) (((elm)->field.cqe_prev == (void *)(head)) ? ((head)->cqh_last) : (elm->field.cqe_prev))trace_printf_helper(level,level_ok,...) trace_printf(__func__, __LINE__, (level), (level_ok), __VA_ARGS__)THREAD_ID_INVALID -1SLIST_HEAD(name,type) struct name { struct type *slh_first; }TEE_PANIC_ID_TEE_COPYOBJECTATTRIBUTES1 0x00000809TEE_MAC_SIZE_DES_CBC_MAC_PKCS5 TEE_Result__ARM_FEATURE_CLZ 1TEE_MATTR_TABLE BIT(3)CONCAT(x,y) _CONCAT(x, y)SPSR_32_AIF_MASK U(0x7)__FLT16_MIN_EXP__ (-13)ESR_EC_AARCH32_CP15_64 U(0x04)getcharCFG_CORE_UNMAP_CORE_AT_EL0 1TCR_XRGNX_WB U(0x1)TEE_MATTR_CACHE_NONCACHE U(0)ESR_FSC_SIZE_L3 U(0x03)__INTMAX_MAX__ 0x7fffffffffffffffL__HAVE_BUILTIN_OVERFLOW 1freeunix 1CIRCLEQ_REMOVE(head,elm,field) do { QUEUEDEBUG_CIRCLEQ_HEAD((head), field) QUEUEDEBUG_CIRCLEQ_ELM((head), (elm), field) if ((elm)->field.cqe_next == (void *)(head)) (head)->cqh_last = (elm)->field.cqe_prev; else (elm)->field.cqe_next->field.cqe_prev = (elm)->field.cqe_prev; if ((elm)->field.cqe_prev == (void *)(head)) (head)->cqh_first = (elm)->field.cqe_next; else (elm)->field.cqe_prev->field.cqe_next = (elm)->field.cqe_next; QUEUEDEBUG_CIRCLEQ_POSTREMOVE((elm), field) } while ( 0)TEE_MEMREF_3_USED 0x00000008TEE_PARAM_TYPE_VALUE_INPUT 1__MM_GENERIC_RAM_LAYOUT_H TEE_PANIC_ID_TEE_SETTAPERSISTENTTIME 0x00001404TEE_PANIC_ID_TEE_GETPROPERTYASUUID 0x00000209ESR_FSC_PERMF_L2 U(0x0e)__cold __attribute__((__cold__))TEE_MEMORY_ACCESS_NONSECURE 0x10000000TEE_PANIC_ID_TEE_FREEPROPERTYENUMERATOR 0x00000202__TEE_MAIN_HASH_SM3 0x7__FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64__DBL_HAS_QUIET_NAN__ 1TEE_ALG_DES3_CMAC 0xF0000613__FLT_EVAL_METHOD__TEE_ATTR_RSA_OAEP_LABEL 0xD0000930KERNEL_USER_TA_H __AARCH64EB____LDBL_EPSILON__ 1.92592994438723585305597794258492732e-34LTEE_LOGIN_USER 0x00000001MEMBER_SIZE(type,member) sizeof(((type *)0)->member)TEE_PANIC_ID_TEE_AEUPDATE 0x00001004__FLT32X_MIN_10_EXP__ (-307)TEE_PANIC_ID_TEE_GETREETIME 0x00001401SCHAR_MIN (-SCHAR_MAX - 1)__unix 1__LDBL_HAS_INFINITY__ 1__DBL_MAX__ ((double)1.79769313486231570814527423731704357e+308L)TEE_ALG_RSASSA_PKCS1_PSS_MGF1_SHA1 0x70212930CFG_TEE_SDP_MEM_SIZE 0x00400000TEE_ALG_HASH_ALGO(main_hash) __tee_alg_hash_algo(main_hash)TLBI_MVA_SHIFT U(12)__FLT16_MIN__ 6.10351562500000000000000000000000000e-5F16__compiler_mul_overflow(a,b,res) __builtin_mul_overflow((a), (b), (res))TEE_PANIC_ID_TEE_OPENPERSISTENTOBJECT 0x00000903CFG_CRYPTOLIB_NAME tomcryptTEE_PANIC_ID_TEE_GETSYSTEMTIME 0x00001402TEE_ALG_SM2_DSA_SM3 0x70006045__FLT_NORM_MAX__ 3.40282346638528859811704183484516925e+38FSIMPLEQ_REMOVE(head,elm,type,field) do { if ((head)->sqh_first == (elm)) { SIMPLEQ_REMOVE_HEAD((head), field); } else { struct type *curelm = (head)->sqh_first; while (curelm->field.sqe_next != (elm)) curelm = curelm->field.sqe_next; if ((curelm->field.sqe_next = curelm->field.sqe_next->field.sqe_next) == NULL) (head)->sqh_last = &(curelm)->field.sqe_next; } } while ( 0)phys_ddr_overall_end SCATTERED_ARRAY_END(phys_ddr_overall, struct core_mmu_phys_mem)TEE_PANIC_ID_TEE_ASYMMETRICSIGNDIGEST 0x00001103ESR_EC_AARCH32_BKPT U(0x38)UINT_FAST8_MAX UINT8_MAXSIMPLEQ_HEAD_INITIALIZER(head) { NULL, &(head).sqh_first }SIMPLEQ_INIT(head) do { (head)->sqh_first = NULL; (head)->sqh_last = &(head)->sqh_first; } while ( 0)ESR_FSC_PERMF_L3 U(0x0f)PRIx8 "x"ROUNDUP_DIV(x,y) (__extension__({ typeof(x) __roundup_x = (x); typeof(y) __roundup_mask = (typeof(x))(y) - 1; (__roundup_x / (y)) + (__roundup_x & __roundup_mask ? 1 : 0); }))TEE_PANIC_ID_TEE_GETTAPERSISTENTTIME 0x00001403__INT_FAST16_TYPE__ long intdt_driverCFG_CORE_ARM64_PA_BITS 32__FLT64_HAS_DENORM__ 1SMSG(...) trace_printf(__func__, __LINE__, TRACE_ERROR, true, __VA_ARGS__)__FLT128_DECIMAL_DIG__ 36CFG_CRYPTO_SHA1 1__FLT_HAS_DENORM__ 1register_dynamic_shm(addr,size) __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), phys_ddr_overall_compat)short intTEE_ALG_GET_KEY_TYPE(algo,with_private_key) __tee_alg_get_key_type(algo, with_private_key)TEE_PANIC_ID_TEE_BIGINTADD 0x00001901UART_LCRH_WLEN_8 (3 << 5)CFG_CRYPTO_SHA256 1TEE_ATTR_RSA_EXPONENT2 0xC0000730TEE_PANIC_ID_TEE_BIGINTCOMPUTEFMM 0x00001C01UART_TIMEOUT 0x0Cphys_mem_map_end SCATTERED_ARRAY_END(phys_mem_map, struct core_mmu_phys_mem)UTEE_DEFINES_H SIMPLEQ_REMOVE_HEAD(head,field) do { if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) (head)->sqh_last = &(head)->sqh_first; } while ( 0)TEE_ERROR_TARGET_DEAD 0xFFFF3024UART_FR_TXFF (1 << 5)TA_RAM_START ROUNDUP(TZDRAM_BASE + TEE_RAM_VA_SIZE, SMALL_PAGE_SIZE)phys_ddr_overall_compat_begin SCATTERED_ARRAY_BEGIN(phys_ddr_overall_compat, struct core_mmu_phys_mem)__compiler_compare_and_swap(p,oval,nval) __atomic_compare_exchange_n((p), (oval), (nval), true, __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)UINTPTR_MAX ULONG_MAXCFG_DEBUG_INFO 1__UINT64_C(c) c ## UL__SIZE_T__ CPACR_EL1_FPEN_NONE U(0x0)TCR_SHX_NSH U(0x0)SMALL_PAGE_MASK ((paddr_t)SMALL_PAGE_SIZE - 1)__LDBL_MANT_DIG__ 113__UINT_LEAST8_TYPE__ unsigned charTAILQ_ENTRY(type) _TAILQ_ENTRY(struct type,)TEE_LOGIN_GROUP 0x00000002pl011_putcTEE_PANIC_ID_TEE_AEENCRYPTFINAL 0x00001002TEE_PANIC_ID_TEE_POPULATETRANSIENTOBJECT 0x00000807TEE_ATTR_SECRET_VALUE 0xC0000000TEE_MATTR_CACHE_CACHED U(1)__register_memory_ul(_name,_type,_addr,_size,_section) __register_memory(_name, _type, _addr, _size, _section)__CHAR16_TYPE__ short unsigned intTEE_ORIGIN_API 0x00000001TEE_PARAM_TYPE_MEMREF_INPUT 5TEE_TYPE_HMAC_SHA256 0xA0000004TCR_IRGN0_SHIFT U(8)TEE_PANIC_ID_TEE_BIGINTSQUAREMOD 0x00001A05UART_CR_OVSFACT (1 << 3)TEE_OPERATION_KEY_DERIVATION 8CIRCLEQ_FOREACH_REVERSE(var,head,field) for ((var) = ((head)->cqh_last); (var) != (const void *)(head); (var) = ((var)->field.cqe_prev))__AARCH64_CMODEL_LARGE__PRIXPTR __PRIPTR_PREFIX "X"TEE_ERROR_SIGNATURE_INVALID 0xFFFF3072__data __section(".data")TAILQ_FOREACH_SAFE(var,head,field,next) for ((var) = ((head)->tqh_first); (var) != NULL && ((next) = TAILQ_NEXT(var, field), 1); (var) = (next))UART_LCRH_BRK (1 << 0)USHRT_MAX (SHRT_MAX * 2 + 1)UTEE_TYPES_H TEE_PANIC_ID_TEE_GETOBJECTVALUEATTRIBUTE 0x00000704TEE_PANIC_ID_TEE_INITREFATTRIBUTE 0x00000805__FLT_EVAL_METHOD_C99__OUTMSG(...) FMSG("< " __VA_ARGS__)__FLT_MIN__ 1.17549435082228750796873653722224568e-38Fpl011_dev_initTEE_ALG_RSASSA_PKCS1_V1_5_MD5SHA1 0x7000F830CFG_WITH_STATS 1__SIZE_TYPE__ long unsigned int__LDBL_MAX_EXP__ 16384__ARM_FEATURE_RNGKEEP_H CSSELR_LEVEL_SHIFT U(1)__GNUC_MINOR__ 2__STDC_UTF_16__ 1_CFG_CORE_LTC_CBC 1TEE_RAM_PH_SIZE TEE_RAM_VA_SIZEDMSG(...) trace_printf_helper(TRACE_DEBUG, true, __VA_ARGS__)_LP64 1UART_ICR 0x44TEE_MAIN_ALGO_SM2_KEP 0x46UINT16_C(v) v__restrict restrictTEE_ALG_RSASSA_PKCS1_V1_5_MD5 0x70001830TEE_U64_TO_BIG_ENDIAN(x) TEE_U64_BSWAP(x)__UINT_FAST32_MAX__ 0xffffffffffffffffUL_CFG_CORE_LTC_CBC_MAC 1TEE_U32_FROM_BIG_ENDIAN(x) TEE_U32_BSWAP(x)ESR_EC_AARCH32_CP15_32 U(0x03)TEE_TYPE_GENERIC_SECRET 0xA0000000__INT_FAST8_WIDTH__ 8__UINTMAX_C(c) c ## ULTEE_ALG_ILLEGAL_VALUE 0xEFFFFFFFDECLARE_KEEP_PAGER(sym) __DECLARE_KEEP_PAGER1(sym, __FILE_ID__)UART_CR_RTS (1 << 11)TEE_PANIC_ID_TA_CREATEENTRYPOINT 0x00000102TAILQ_LAST(head,headname) (*(((struct headname *)((head)->tqh_last))->tqh_last))_STDARG_H SLIST_NEXT(elm,field) ((elm)->field.sle_next)__PTRDIFF_TYPE__ long intMIN_UNSAFE(a,b) (((a) < (b)) ? (a) : (b))_CFG_CORE_LTC_ECB 1__UINT_LEAST8_MAX__ 0xff__FLT32_NORM_MAX__ 3.40282346638528859811704183484516925e+38F32TEE_PANIC_ID_TEE_ASYMMETRICENCRYPT 0x00001102BIT64(nr) (UINT64_C(1) << (nr))__FLT32X_MIN__ 2.22507385850720138309023271733240406e-308F32x__INT64_C(c) c ## L__FLT64X_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F64xTEE_ALG_HKDF_SHA224_DERIVE_KEY 0x800030C0tee_vbuf_is core_vbuf_isCMP_TRILEAN(a,b) (__extension__({ __typeof__(a) _a = (a); __typeof__(b) _b = (b); _a > _b ? 1 : _a < _b ? -1 : 0; }))SCTLR_WXN BIT32(19)core/drivers/pl011.cCFG_CORE_TZSRAM_EMUL_SIZE 458752TEE_TYPE_RSA_KEYPAIR 0xA1000030__DBL_NORM_MAX__ ((double)1.79769313486231570814527423731704357e+308L)TEE_USAGE_EXTRACTABLE 0x00000001read_mpidr() read_mpidr_el1()GCC: (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103zRx (AF8L$AG l4A CH,AI DA CL$A0BCZ$A@BCk,-./ / /(1 113 3.3$5 5>547 7I7,9 9U9D; ;=> >c>@ArAuACrCC ErEE GGHrHH(JrJLNOQSUrWY[]_acegikmoqsuwy{}NH y    Aq@yP~ =n !G"#$%*&a'()* +      !"#$%&'()*+L )X _ ;j w   Jpl011.c$xpl011_have_rx_datapl011_dev_freepl011_dev_allocpl011_putcpl011_flushpl011_getcharpl011_dev_init$dpl011_driverpl011_match_tablepl011_ops__func__.0__scattered_array_0dt_driverswm4.0.0c2757927af938237dad2538743df18cwm4.conf.h.2.27a59c4a24628c7694563cf161b1456awm4.compiler.h.7.ff8c7af35a6a55f407776d82ff392a74wm4.stdarg.h.31.b55da1089056868966f25de5dbfc7d3cwm4.stdbool.h.29.07dce69c3b78884144b7f7bd19483461wm4.stddef.h.39.27677723d43e5b5a7afdf8d798429f1dwm4.trace_levels.h.6.505d35da271c0597dd2f84103d342d6bwm4.trace.h.14.e67646cb777e7100284aeacbea3e9bf6wm4.assert.h.19.d5c5642ae191d5539a96347cd4ce4641wm4.limits.h.6.1223e95d2c07729a89d61368528e351awm4.stdint.h.14.7254d4ddddc405ae01d91db8729516ebwm4.inttypes.h.14.04e955cd15f1a1b81e8c7d766922740bwm4.types_ext.h.15.e3b47cfc410272ddfab11b3a34a626a6wm4.queue.h.36.ab6be41b80585ec9d579ac4c6beceb1awm4.mutex.h.19.84c9e3da130860eb4fcd62ac4b5ced1cwm4.malloc.h.15.6930c05677ba761883918ce0ce0a01e3wm4.tee_common.h.32.e3e16e2e9a1728f6eed2b7aa0525ca57wm4.tee_api_defines.h.9.15bfa1d81f385075137a5e5cb1dad104wm4.tee_api_types.h.195.70f88af562e4de06db5cb96bde92609fwm4.util.h.6.47b426b7fb0b49a5af30a0a0aaf8ca95wm4.tee_mmu_types.h.13.624c3fdf45855b0b423b12d06488817ewm4.user_ta_header.h.8.3a4ff74d5df5bf852dbc28541e19c80dwm4.tee_ta_manager.h.23.ef4eba23024ac593234d709a7038a9e7wm4.arm.h.14.39e7a889303dc796aee3ff42ba52f4bawm4.cdefs.h.6.216810ff45474094d4f2557fb832b9f7wm4.arm64.h.13.9d46b807ffcce55097702b988c2f7802wm4.vfp.h.7.fe67ebea0cc1b7ee2a8a6728776897d2wm4.pgt_cache.h.6.b2c9c7095bc5ee0a1d7e21232274ef1awm4.thread.h.20.e21d0b96e9dd6036398126832bea4508wm4.tee_api_defines_extensions.h.8.4f014b668a58a53beba9a565b7ccfcdewm4.utee_defines.h.18.c17b9403052b06642cb6b8e2e294c31ewm4.tee_mm.h.7.c53beb94045541f300207b891a1fd448wm4.keep.h.6.9f0c7528dcb60415bbe8e7882a4c8945wm4.scattered_array.h.20.4dc4f3101b01436b2dcd3d8dd7027d2bwm4.generic_ram_layout.h.7.a8dcff79550ff350306bc057f3cb3704wm4.platform_config.h.13.a671eb1fadb3007f04e4b688e58db314wm4.core_mmu.h.21.013b2772117952686470033a5d05ef06wm4.core_memprot.h.37.3afeecc86f1b618c850acd9dc9bf7461wm4.io.h.20.c33925fa09ec7443de46cce8cc3222ffwm4.irq.h.11.75b56693222fe0cb196abaf61ae51201wm4.interrupt.h.13.c460c33872e2a4f8087daadeeb572fc0wm4.panic.h.7.f5c3f988cceec4e64da73765d40668a8wm4.dt.h.22.026e100aed62e19477dd2d7c2f645694io_pa_or_vacallocpl011_inittrace_printfdt_map_devvirt_to_phys____keep_pager_pl011_ops_core_drivers_pl011_c$ $$$0,0'48'H\p&t'x&|' !$/ 55/5Φ2P%4)3056>5-C5kQ56]5i5np5w5;H~5[555ԫ5p5I 55455a&5ќ35"@5rM5z5i5550&5E35@5+N5@[5Gh5m`{5r5ș5d5H5e455 55]5 5V5,$55rBK5|Xv5 !5 )55+000Z0T590 055*)@W5+b0f0v0Xz0R5k005,000L0H5E50055'2 5900L2'O``'&5% 3070< U5H\}0B0:5005005l0N0H500@5\00L L(0,050+90)CTLTd0Rh0Pq0wu0u440000880000X 20806&0_*0]4d=dY0]0f0j0tl}l000045{$ 5+ 0' 0!# 0{' 0u, 57 0; 0D M 2@] 0a 0f 2@o 0Ds 0>|  0 0    0 0 $ $ 0  0 $ 06 ( 04 / 5: Q 5+\ 0_ ` 0Y e 5p 0 t 0 }  2 0 0 2 0' 0  0 0  0 0 0 " 0 ( (= 5_ H _ 5+j 0 n 0 s 5~ 0Y 0W  2 0 0| 2 0 0  0, 0&   + 0| / 0z 6 5n= T 5+_ 0 c 0 h 5s 0 w 0  2 0 0 2 0t 0n  0 0   $ 0( 02 ; S 0AW 0?^ 5o 5+ 59 5х 5q 5 5q 5& 5& 5 5 5' 5' 5454 5 555!.6Zbow $$,4X`HkHs~DD@@K"K*LT_g$$  BJ3U3]|h|p}$$3333D"D*NV3a3i`t`|4xHTTXLP+L3PRTZXwPX48488<8<8X@d_Xgddldlltlt'/:BOW4{,,44  DLYalt44  $ (6 $> (_ g r z 8 8 D    8     ' / < D O W 8d 8l D    8 8 D 0 4     $ 1 9 (Y a             (, 4  ?  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