αsphinx.addnodesdocument)}( rawsourcechildren](docutils.nodessubstitution_definition)}(h&.. |AArch32| replace:: :term:`AArch32`h]h pending_xref)}(h:term:`AArch32`h]h inline)}(hhh]h TextAArch32}(hhparenthuba attributes}(ids]classes](xrefstdstd-termenames]dupnames]backrefs]utagnamehh!hubah"}(h$]h&]h+]h-]h/]refdocplat/arm/arm_fpga/index refdomainh)reftypeterm refexplicitrefwarn reftargetAArch32uh1hsource lineKh!h ubah"}(h$]h&]h+]AArch32ah-]h/]uh1h hAhBhCKh!hhhubh )}(h&.. |AArch64| replace:: :term:`AArch64`h]h)}(h:term:`AArch64`h]h)}(hhQh]hAArch64}(hhh!hSubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!hOubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainh]reftypeterm refexplicitrefwarnh?AArch64uh1hhAhBhCKh!hKubah"}(h$]h&]h+]AArch64ah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |AMU| replace:: :term:`AMU`h]h)}(h :term:`AMU`h]h)}(hh|h]hAMU}(hhh!h~ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!hzubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainhreftypeterm refexplicitrefwarnh?AMUuh1hhAhBhCKh!hvubah"}(h$]h&]h+]AMUah-]h/]uh1h hAhBhCKh!hhhubh )}(h&.. |AMUs| replace:: :term:`AMUs `h]h)}(h:term:`AMUs `h]h)}(hhh]hAMUs}(hhh!hubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!hubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainhreftypeterm refexplicitrefwarnh?AMUuh1hhAhBhCKh!hubah"}(h$]h&]h+]AMUsah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |API| replace:: :term:`API`h]h)}(h :term:`API`h]h)}(hhh]hAPI}(hhh!hubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!hubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainhތreftypeterm refexplicitrefwarnh?APIuh1hhAhBhCKh!hubah"}(h$]h&]h+]APIah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |BTI| replace:: :term:`BTI`h]h)}(h :term:`BTI`h]h)}(hhh]hBTI}(hhh!hubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!hubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?BTIuh1hhAhBhCKh!hubah"}(h$]h&]h+]BTIah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |CoT| replace:: :term:`CoT`h]h)}(h :term:`CoT`h]h)}(hj(h]hCoT}(hhh!j*ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j&ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj4reftypeterm refexplicitrefwarnh?CoTuh1hhAhBhCKh!j"ubah"}(h$]h&]h+]CoTah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |COT| replace:: :term:`COT`h]h)}(h :term:`COT`h]h)}(hjSh]hCOT}(hhh!jUubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jQubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj_reftypeterm refexplicitrefwarnh?COTuh1hhAhBhCKh!jMubah"}(h$]h&]h+]COTah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |CSS| replace:: :term:`CSS`h]h)}(h :term:`CSS`h]h)}(hj~h]hCSS}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j|ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?CSSuh1hhAhBhCK h!jxubah"}(h$]h&]h+]CSSah-]h/]uh1h hAhBhCK h!hhhubh )}(h.. |CVE| replace:: :term:`CVE`h]h)}(h :term:`CVE`h]h)}(hjh]hCVE}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?CVEuh1hhAhBhCK h!jubah"}(h$]h&]h+]CVEah-]h/]uh1h hAhBhCK h!hhhubh )}(h.. |DTB| replace:: :term:`DTB`h]h)}(h :term:`DTB`h]h)}(hjh]hDTB}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?DTBuh1hhAhBhCK h!jubah"}(h$]h&]h+]DTBah-]h/]uh1h hAhBhCK h!hhhubh )}(h .. |DS-5| replace:: :term:`DS-5`h]h)}(h :term:`DS-5`h]h)}(hjh]hDS-5}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?DS-5uh1hhAhBhCK h!jubah"}(h$]h&]h+]DS-5ah-]h/]uh1h hAhBhCK h!hhhubh )}(h.. |DSU| replace:: :term:`DSU`h]h)}(h :term:`DSU`h]h)}(hj*h]hDSU}(hhh!j,ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j(ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj6reftypeterm refexplicitrefwarnh?DSUuh1hhAhBhCK h!j$ubah"}(h$]h&]h+]DSUah-]h/]uh1h hAhBhCK h!hhhubh )}(h.. |DT| replace:: :term:`DT`h]h)}(h :term:`DT`h]h)}(hjUh]hDT}(hhh!jWubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jSubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjareftypeterm refexplicitrefwarnh?DTuh1hhAhBhCKh!jOubah"}(h$]h&]h+]DTah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |EL| replace:: :term:`EL`h]h)}(h :term:`EL`h]h)}(hjh]hEL}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j~ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?ELuh1hhAhBhCKh!jzubah"}(h$]h&]h+]ELah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |EHF| replace:: :term:`EHF`h]h)}(h :term:`EHF`h]h)}(hjh]hEHF}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?EHFuh1hhAhBhCKh!jubah"}(h$]h&]h+]EHFah-]h/]uh1h hAhBhCKh!hhhubh )}(h".. |FCONF| replace:: :term:`FCONF`h]h)}(h :term:`FCONF`h]h)}(hjh]hFCONF}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?FCONFuh1hhAhBhCKh!jubah"}(h$]h&]h+]FCONFah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |FDT| replace:: :term:`FDT`h]h)}(h :term:`FDT`h]h)}(hjh]hFDT}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?FDTuh1hhAhBhCKh!jubah"}(h$]h&]h+]FDTah-]h/]uh1h hAhBhCKh!hhhubh )}(h .. |FF-A| replace:: :term:`FF-A`h]h)}(h :term:`FF-A`h]h)}(hj,h]hFF-A}(hhh!j.ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j*ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj8reftypeterm refexplicitrefwarnh?FF-Auh1hhAhBhCKh!j&ubah"}(h$]h&]h+]FF-Aah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |FIP| replace:: :term:`FIP`h]h)}(h :term:`FIP`h]h)}(hjWh]hFIP}(hhh!jYubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jUubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjcreftypeterm refexplicitrefwarnh?FIPuh1hhAhBhCKh!jQubah"}(h$]h&]h+]FIPah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |FVP| replace:: :term:`FVP`h]h)}(h :term:`FVP`h]h)}(hjh]hFVP}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?FVPuh1hhAhBhCKh!j|ubah"}(h$]h&]h+]FVPah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |FWU| replace:: :term:`FWU`h]h)}(h :term:`FWU`h]h)}(hjh]hFWU}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?FWUuh1hhAhBhCKh!jubah"}(h$]h&]h+]FWUah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |GIC| replace:: :term:`GIC`h]h)}(h :term:`GIC`h]h)}(hjh]hGIC}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?GICuh1hhAhBhCKh!jubah"}(h$]h&]h+]GICah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |ISA| replace:: :term:`ISA`h]h)}(h :term:`ISA`h]h)}(hjh]hISA}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?ISAuh1hhAhBhCKh!jubah"}(h$]h&]h+]ISAah-]h/]uh1h hAhBhCKh!hhhubh )}(h$.. |Linaro| replace:: :term:`Linaro`h]h)}(h:term:`Linaro`h]h)}(hj.h]hLinaro}(hhh!j0ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j,ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj:reftypeterm refexplicitrefwarnh?Linarouh1hhAhBhCKh!j(ubah"}(h$]h&]h+]Linaroah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |MMU| replace:: :term:`MMU`h]h)}(h :term:`MMU`h]h)}(hjYh]hMMU}(hhh!j[ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jWubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjereftypeterm refexplicitrefwarnh?MMUuh1hhAhBhCKh!jSubah"}(h$]h&]h+]MMUah-]h/]uh1h hAhBhCKh!hhhubh )}(h .. |MPAM| replace:: :term:`MPAM`h]h)}(h :term:`MPAM`h]h)}(hjh]hMPAM}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?MPAMuh1hhAhBhCKh!j~ubah"}(h$]h&]h+]MPAMah-]h/]uh1h hAhBhCKh!hhhubh )}(h .. |MPMM| replace:: :term:`MPMM`h]h)}(h :term:`MPMM`h]h)}(hjh]hMPMM}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?MPMMuh1hhAhBhCKh!jubah"}(h$]h&]h+]MPMMah-]h/]uh1h hAhBhCKh!hhhubh )}(h".. |MPIDR| replace:: :term:`MPIDR`h]h)}(h :term:`MPIDR`h]h)}(hjh]hMPIDR}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?MPIDRuh1hhAhBhCKh!jubah"}(h$]h&]h+]MPIDRah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |MTE| replace:: :term:`MTE`h]h)}(h :term:`MTE`h]h)}(hjh]hMTE}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?MTEuh1hhAhBhCKh!jubah"}(h$]h&]h+]MTEah-]h/]uh1h hAhBhCKh!hhhubh )}(h.. |OEN| replace:: :term:`OEN`h]h)}(h :term:`OEN`h]h)}(hj0h]hOEN}(hhh!j2ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j.ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj<reftypeterm refexplicitrefwarnh?OENuh1hhAhBhCKh!j*ubah"}(h$]h&]h+]OENah-]h/]uh1h hAhBhCKh!hhhubh )}(h$.. |OP-TEE| replace:: :term:`OP-TEE`h]h)}(h:term:`OP-TEE`h]h)}(hj[h]hOP-TEE}(hhh!j]ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jYubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjgreftypeterm refexplicitrefwarnh?OP-TEEuh1hhAhBhCK h!jUubah"}(h$]h&]h+]OP-TEEah-]h/]uh1h hAhBhCK h!hhhubh )}(h.. |OTE| replace:: :term:`OTE`h]h)}(h :term:`OTE`h]h)}(hjh]hOTE}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?OTEuh1hhAhBhCK!h!jubah"}(h$]h&]h+]OTEah-]h/]uh1h hAhBhCK!h!hhhubh )}(h.. |PDD| replace:: :term:`PDD`h]h)}(h :term:`PDD`h]h)}(hjh]hPDD}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?PDDuh1hhAhBhCK"h!jubah"}(h$]h&]h+]PDDah-]h/]uh1h hAhBhCK"h!hhhubh )}(h".. |PAUTH| replace:: :term:`PAUTH`h]h)}(h :term:`PAUTH`h]h)}(hjh]hPAUTH}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?PAUTHuh1hhAhBhCK#h!jubah"}(h$]h&]h+]PAUTHah-]h/]uh1h hAhBhCK#h!hhhubh )}(h.. |PMF| replace:: :term:`PMF`h]h)}(h :term:`PMF`h]h)}(hjh]hPMF}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?PMFuh1hhAhBhCK$h!jubah"}(h$]h&]h+]PMFah-]h/]uh1h hAhBhCK$h!hhhubh )}(h .. |PSCI| replace:: :term:`PSCI`h]h)}(h :term:`PSCI`h]h)}(hj2h]hPSCI}(hhh!j4ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j0ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj>reftypeterm refexplicitrefwarnh?PSCIuh1hhAhBhCK%h!j,ubah"}(h$]h&]h+]PSCIah-]h/]uh1h hAhBhCK%h!hhhubh )}(h.. |RAS| replace:: :term:`RAS`h]h)}(h :term:`RAS`h]h)}(hj]h]hRAS}(hhh!j_ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j[ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjireftypeterm refexplicitrefwarnh?RASuh1hhAhBhCK&h!jWubah"}(h$]h&]h+]RASah-]h/]uh1h hAhBhCK&h!hhhubh )}(h.. |ROT| replace:: :term:`ROT`h]h)}(h :term:`ROT`h]h)}(hjh]hROT}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?ROTuh1hhAhBhCK'h!jubah"}(h$]h&]h+]ROTah-]h/]uh1h hAhBhCK'h!hhhubh )}(h .. |SCMI| replace:: :term:`SCMI`h]h)}(h :term:`SCMI`h]h)}(hjh]hSCMI}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SCMIuh1hhAhBhCK(h!jubah"}(h$]h&]h+]SCMIah-]h/]uh1h hAhBhCK(h!hhhubh )}(h.. |SCP| replace:: :term:`SCP`h]h)}(h :term:`SCP`h]h)}(hjh]hSCP}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SCPuh1hhAhBhCK)h!jubah"}(h$]h&]h+]SCPah-]h/]uh1h hAhBhCK)h!hhhubh )}(h .. |SDEI| replace:: :term:`SDEI`h]h)}(h :term:`SDEI`h]h)}(hj h]hSDEI}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SDEIuh1hhAhBhCK*h!jubah"}(h$]h&]h+]SDEIah-]h/]uh1h hAhBhCK*h!hhhubh )}(h.. |SDS| replace:: :term:`SDS`h]h)}(h :term:`SDS`h]h)}(hj4h]hSDS}(hhh!j6ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j2ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj@reftypeterm refexplicitrefwarnh?SDSuh1hhAhBhCK+h!j.ubah"}(h$]h&]h+]SDSah-]h/]uh1h hAhBhCK+h!hhhubh )}(h.. |SEA| replace:: :term:`SEA`h]h)}(h :term:`SEA`h]h)}(hj_h]hSEA}(hhh!jaubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j]ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjkreftypeterm refexplicitrefwarnh?SEAuh1hhAhBhCK,h!jYubah"}(h$]h&]h+]SEAah-]h/]uh1h hAhBhCK,h!hhhubh )}(h.. |SiP| replace:: :term:`SiP`h]h)}(h :term:`SiP`h]h)}(hjh]hSiP}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SiPuh1hhAhBhCK-h!jubah"}(h$]h&]h+]SiPah-]h/]uh1h hAhBhCK-h!hhhubh )}(h.. |SIP| replace:: :term:`SIP`h]h)}(h :term:`SIP`h]h)}(hjh]hSIP}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SIPuh1hhAhBhCK.h!jubah"}(h$]h&]h+]SIPah-]h/]uh1h hAhBhCK.h!hhhubh )}(h.. |SMC| replace:: :term:`SMC`h]h)}(h :term:`SMC`h]h)}(hjh]hSMC}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SMCuh1hhAhBhCK/h!jubah"}(h$]h&]h+]SMCah-]h/]uh1h hAhBhCK/h!hhhubh )}(h".. |SMCCC| replace:: :term:`SMCCC`h]h)}(h :term:`SMCCC`h]h)}(hj h]hSMCCC}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SMCCCuh1hhAhBhCK0h!jubah"}(h$]h&]h+]SMCCCah-]h/]uh1h hAhBhCK0h!hhhubh )}(h.. |SoC| replace:: :term:`SoC`h]h)}(h :term:`SoC`h]h)}(hj6h]hSoC}(hhh!j8ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j4ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjBreftypeterm refexplicitrefwarnh?SoCuh1hhAhBhCK1h!j0ubah"}(h$]h&]h+]SoCah-]h/]uh1h hAhBhCK1h!hhhubh )}(h.. |SP| replace:: :term:`SP`h]h)}(h :term:`SP`h]h)}(hjah]hSP}(hhh!jcubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j_ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjmreftypeterm refexplicitrefwarnh?SPuh1hhAhBhCK2h!j[ubah"}(h$]h&]h+]SPah-]h/]uh1h hAhBhCK2h!hhhubh )}(h.. |SPD| replace:: :term:`SPD`h]h)}(h :term:`SPD`h]h)}(hjh]hSPD}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SPDuh1hhAhBhCK3h!jubah"}(h$]h&]h+]SPDah-]h/]uh1h hAhBhCK3h!hhhubh )}(h.. |SPM| replace:: :term:`SPM`h]h)}(h :term:`SPM`h]h)}(hjh]hSPM}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SPMuh1hhAhBhCK4h!jubah"}(h$]h&]h+]SPMah-]h/]uh1h hAhBhCK4h!hhhubh )}(h .. |SSBS| replace:: :term:`SSBS`h]h)}(h :term:`SSBS`h]h)}(hjh]hSSBS}(hhh!jubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!jubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjreftypeterm refexplicitrefwarnh?SSBSuh1hhAhBhCK5h!jubah"}(h$]h&]h+]SSBSah-]h/]uh1h hAhBhCK5h!hhhubh )}(h.. |SVE| replace:: :term:`SVE`h]h)}(h :term:`SVE`h]h)}(hj h]hSVE}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?SVEuh1hhAhBhCK6h!j ubah"}(h$]h&]h+]SVEah-]h/]uh1h hAhBhCK6h!hhhubh )}(h.. |TBB| replace:: :term:`TBB`h]h)}(h :term:`TBB`h]h)}(hj8 h]hTBB}(hhh!j: ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j6 ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjD reftypeterm refexplicitrefwarnh?TBBuh1hhAhBhCK7h!j2 ubah"}(h$]h&]h+]TBBah-]h/]uh1h hAhBhCK7h!hhhubh )}(h .. |TBBR| replace:: :term:`TBBR`h]h)}(h :term:`TBBR`h]h)}(hjc h]hTBBR}(hhh!je ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!ja ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjo reftypeterm refexplicitrefwarnh?TBBRuh1hhAhBhCK8h!j] ubah"}(h$]h&]h+]TBBRah-]h/]uh1h hAhBhCK8h!hhhubh )}(h.. |TEE| replace:: :term:`TEE`h]h)}(h :term:`TEE`h]h)}(hj h]hTEE}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?TEEuh1hhAhBhCK9h!j ubah"}(h$]h&]h+]TEEah-]h/]uh1h hAhBhCK9h!hhhubh )}(h .. |TF-A| replace:: :term:`TF-A`h]h)}(h :term:`TF-A`h]h)}(hj h]hTF-A}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?TF-Auh1hhAhBhCK:h!j ubah"}(h$]h&]h+]TF-Aah-]h/]uh1h hAhBhCK:h!hhhubh )}(h .. |TF-M| replace:: :term:`TF-M`h]h)}(h :term:`TF-M`h]h)}(hj h]hTF-M}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?TF-Muh1hhAhBhCK;h!j ubah"}(h$]h&]h+]TF-Mah-]h/]uh1h hAhBhCK;h!hhhubh )}(h.. |TLB| replace:: :term:`TLB`h]h)}(h :term:`TLB`h]h)}(hj h]hTLB}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?TLBuh1hhAhBhCKh!j_ ubah"}(h$]h&]h+]TRNGah-]h/]uh1h hAhBhCK>h!hhhubh )}(h.. |TSP| replace:: :term:`TSP`h]h)}(h :term:`TSP`h]h)}(hj h]hTSP}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?TSPuh1hhAhBhCK?h!j ubah"}(h$]h&]h+]TSPah-]h/]uh1h hAhBhCK?h!hhhubh )}(h.. |TZC| replace:: :term:`TZC`h]h)}(h :term:`TZC`h]h)}(hj h]hTZC}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?TZCuh1hhAhBhCK@h!j ubah"}(h$]h&]h+]TZCah-]h/]uh1h hAhBhCK@h!hhhubh )}(h".. |UBSAN| replace:: :term:`UBSAN`h]h)}(h :term:`UBSAN`h]h)}(hj h]hUBSAN}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?UBSANuh1hhAhBhCKAh!j ubah"}(h$]h&]h+]UBSANah-]h/]uh1h hAhBhCKAh!hhhubh )}(h .. |UEFI| replace:: :term:`UEFI`h]h)}(h :term:`UEFI`h]h)}(hj h]hUEFI}(hhh!j ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainj reftypeterm refexplicitrefwarnh?UEFIuh1hhAhBhCKBh!j ubah"}(h$]h&]h+]UEFIah-]h/]uh1h hAhBhCKBh!hhhubh )}(h .. |WDOG| replace:: :term:`WDOG`h]h)}(h :term:`WDOG`h]h)}(hj< h]hWDOG}(hhh!j> ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!j: ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjH reftypeterm refexplicitrefwarnh?WDOGuh1hhAhBhCKCh!j6 ubah"}(h$]h&]h+]WDOGah-]h/]uh1h hAhBhCKCh!hhhubh )}(h!.. |XLAT| replace:: :term:`XLAT` h]h)}(h :term:`XLAT`h]h)}(hjg h]hXLAT}(hhh!ji ubah"}(h$]h&](h(stdstd-termeh+]h-]h/]uh1hh!je ubah"}(h$]h&]h+]h-]h/]refdoch9 refdomainjs reftypeterm refexplicitrefwarnh?XLATuh1hhAhBhCKDh!ja ubah"}(h$]h&]h+]XLATah-]h/]uh1h hAhBhCKDh!hhhubh section)}(hhh](h title)}(hArm FPGA Platformh]hArm FPGA Platform}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAX/home/test/workspace/code/optee_3.16/trusted-firmware-a/docs/plat/arm/arm_fpga/index.rsthCKubh paragraph)}(hXThis platform supports FPGA images used internally in Arm Ltd., for testing and bringup of new cores. With that focus, peripheral support is minimal: there is no mass storage or display output, for instance. Also this port ignores any power management features of the platform. Some interconnect setup is done internally by the platform, so the TF-A code just needs to setup UART and GIC.h]hXThis platform supports FPGA images used internally in Arm Ltd., for testing and bringup of new cores. With that focus, peripheral support is minimal: there is no mass storage or display output, for instance. Also this port ignores any power management features of the platform. Some interconnect setup is done internally by the platform, so the TF-A code just needs to setup UART and GIC.}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j hAj hCKh!j hhubj )}(hThe FPGA platform requires to pass on a DTB for the non-secure payload (mostly Linux), so we let TF-A use information from the DTB for dynamic configuration: the UART and GIC base addresses are read from there.h]hThe FPGA platform requires to pass on a DTB for the non-secure payload (mostly Linux), so we let TF-A use information from the DTB for dynamic configuration: the UART and GIC base addresses are read from there.}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j hAj hCK h!j hhubj )}(hAs a result this port is a fairly generic BL31-only port, which can serve as a template for a minimal new (and possibly DT-based) platform port.h]hAs a result this port is a fairly generic BL31-only port, which can serve as a template for a minimal new (and possibly DT-based) platform port.}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j hAj hCKh!j hhubj )}(hThe aim of this port is to support as many FPGA images as possible with a single build. Image specific data must be described in the DTB or should be auto-detected at runtime.h]hThe aim of this port is to support as many FPGA images as possible with a single build. Image specific data must be described in the DTB or should be auto-detected at runtime.}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j hAj hCKh!j hhubj )}(hAs the number and topology layout of the CPU cores differs significantly across the various images, this is detected at runtime by BL31. The /cpus node in the DT will be added and filled accordingly, as long as it does not exist already.h]hAs the number and topology layout of the CPU cores differs significantly across the various images, this is detected at runtime by BL31. The /cpus node in the DT will be added and filled accordingly, as long as it does not exist already.}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j hAj hCKh!j hhubj )}(hhh](j )}(hPlatform-specific build optionsh]hPlatform-specific build options}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAj hCKubh bullet_list)}(hhh](h list_item)}(hX``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers. Normally TF-A panics if it encounters a MPID value not matched to its internal list, but for new or experimental cores this creates a lot of churn. With this option, the code will fall back to some basic CPU support code (only architectural system registers, and no errata). Default value of this flag is 1. h]j )}(hX``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers. Normally TF-A panics if it encounters a MPID value not matched to its internal list, but for new or experimental cores this creates a lot of churn. With this option, the code will fall back to some basic CPU support code (only architectural system registers, and no errata). Default value of this flag is 1.h](h literal)}(h``SUPPORT_UNKNOWN_MPID``h]hSUPPORT_UNKNOWN_MPID}(hhh!j ubah"}(h$]h&]h+]h-]h/]uh1j h!j ubhXg : Boolean option to allow unknown MPIDR registers. Normally TF-A panics if it encounters a MPID value not matched to its internal list, but for new or experimental cores this creates a lot of churn. With this option, the code will fall back to some basic CPU support code (only architectural system registers, and no errata). Default value of this flag is 1.}(hXg : Boolean option to allow unknown MPIDR registers. Normally TF-A panics if it encounters a MPID value not matched to its internal list, but for new or experimental cores this creates a lot of churn. With this option, the code will fall back to some basic CPU support code (only architectural system registers, and no errata). Default value of this flag is 1.h!j ubeh"}(h$]h&]h+]h-]h/]uh1j hAj hCKh!j ubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAj hCNubj )}(hX``PRELOADED_BL33_BASE`` : Physical address of the BL33 non-secure payload. It must have been loaded into DRAM already, typically this is done by the script that also loads BL31 and the DTB. It defaults to 0x80080000, which is the traditional load address for an arm64 Linux kernel. h]j )}(hX``PRELOADED_BL33_BASE`` : Physical address of the BL33 non-secure payload. It must have been loaded into DRAM already, typically this is done by the script that also loads BL31 and the DTB. It defaults to 0x80080000, which is the traditional load address for an arm64 Linux kernel.h](j )}(h``PRELOADED_BL33_BASE``h]hPRELOADED_BL33_BASE}(hhh!j3 ubah"}(h$]h&]h+]h-]h/]uh1j h!j/ ubhX : Physical address of the BL33 non-secure payload. It must have been loaded into DRAM already, typically this is done by the script that also loads BL31 and the DTB. It defaults to 0x80080000, which is the traditional load address for an arm64 Linux kernel.}(hX : Physical address of the BL33 non-secure payload. It must have been loaded into DRAM already, typically this is done by the script that also loads BL31 and the DTB. It defaults to 0x80080000, which is the traditional load address for an arm64 Linux kernel.h!j/ ubeh"}(h$]h&]h+]h-]h/]uh1j hAj hCK%h!j+ ubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAj hCNubj )}(hX ``FPGA_PRELOADED_DTB_BASE`` : Physical address of the flattened device tree blob (DTB). This DT will be used by TF-A for dynamic configuration, so it must describe at least the UART and a GICv3 interrupt controller. The DT gets amended by the code, to potentially add a command line and fill the CPU topology nodes. It will also be passed on to BL33, by putting its address into the x0 register before jumping to the entry point (following the Linux kernel boot protocol). It defaults to 0x80070000, which is 64KB before the BL33 load address. h]j )}(hX``FPGA_PRELOADED_DTB_BASE`` : Physical address of the flattened device tree blob (DTB). This DT will be used by TF-A for dynamic configuration, so it must describe at least the UART and a GICv3 interrupt controller. The DT gets amended by the code, to potentially add a command line and fill the CPU topology nodes. It will also be passed on to BL33, by putting its address into the x0 register before jumping to the entry point (following the Linux kernel boot protocol). It defaults to 0x80070000, which is 64KB before the BL33 load address.h](j )}(h``FPGA_PRELOADED_DTB_BASE``h]hFPGA_PRELOADED_DTB_BASE}(hhh!jZ ubah"}(h$]h&]h+]h-]h/]uh1j h!jV ubhX : Physical address of the flattened device tree blob (DTB). This DT will be used by TF-A for dynamic configuration, so it must describe at least the UART and a GICv3 interrupt controller. The DT gets amended by the code, to potentially add a command line and fill the CPU topology nodes. It will also be passed on to BL33, by putting its address into the x0 register before jumping to the entry point (following the Linux kernel boot protocol). It defaults to 0x80070000, which is 64KB before the BL33 load address.}(hX : Physical address of the flattened device tree blob (DTB). This DT will be used by TF-A for dynamic configuration, so it must describe at least the UART and a GICv3 interrupt controller. The DT gets amended by the code, to potentially add a command line and fill the CPU topology nodes. It will also be passed on to BL33, by putting its address into the x0 register before jumping to the entry point (following the Linux kernel boot protocol). It defaults to 0x80070000, which is 64KB before the BL33 load address.h!jV ubeh"}(h$]h&]h+]h-]h/]uh1j hAj hCK+h!jR ubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAj hCNubj )}(hX``FPGA_PRELOADED_CMD_LINE`` : Physical address of the command line to put into the devicetree blob. Due to the lack of a proper bootloader, a command line can be put somewhere into memory, so that BL31 will detect it and copy it into the DTB passed on to BL33. To avoid random garbage, there needs to be a "CMD:" signature before the actual command line. Defaults to 0x1000, which is normally in the "ROM" space of the typical FPGA image (which can be written by the FPGA payload uploader, but is read-only to the CPU). The FPGA payload tool should be given a text file containing the desired command line, prefixed by the "CMD:" signature. h]j )}(hX``FPGA_PRELOADED_CMD_LINE`` : Physical address of the command line to put into the devicetree blob. Due to the lack of a proper bootloader, a command line can be put somewhere into memory, so that BL31 will detect it and copy it into the DTB passed on to BL33. To avoid random garbage, there needs to be a "CMD:" signature before the actual command line. Defaults to 0x1000, which is normally in the "ROM" space of the typical FPGA image (which can be written by the FPGA payload uploader, but is read-only to the CPU). The FPGA payload tool should be given a text file containing the desired command line, prefixed by the "CMD:" signature.h](j )}(h``FPGA_PRELOADED_CMD_LINE``h]hFPGA_PRELOADED_CMD_LINE}(hhh!j ubah"}(h$]h&]h+]h-]h/]uh1j h!j} ubhXq : Physical address of the command line to put into the devicetree blob. Due to the lack of a proper bootloader, a command line can be put somewhere into memory, so that BL31 will detect it and copy it into the DTB passed on to BL33. To avoid random garbage, there needs to be a “CMD:” signature before the actual command line. Defaults to 0x1000, which is normally in the “ROM” space of the typical FPGA image (which can be written by the FPGA payload uploader, but is read-only to the CPU). The FPGA payload tool should be given a text file containing the desired command line, prefixed by the “CMD:” signature.}(hXe : Physical address of the command line to put into the devicetree blob. Due to the lack of a proper bootloader, a command line can be put somewhere into memory, so that BL31 will detect it and copy it into the DTB passed on to BL33. To avoid random garbage, there needs to be a "CMD:" signature before the actual command line. Defaults to 0x1000, which is normally in the "ROM" space of the typical FPGA image (which can be written by the FPGA payload uploader, but is read-only to the CPU). The FPGA payload tool should be given a text file containing the desired command line, prefixed by the "CMD:" signature.h!j} ubeh"}(h$]h&]h+]h-]h/]uh1j hAj hCK4h!jy ubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAj hCNubeh"}(h$]h&]h+]h-]h/]bullet-uh1j hAj hCKh!j hhubeh"}(h$]platform-specific-build-optionsah&]h+]platform-specific build optionsah-]h/]uh1j h!j hhhAj hCKubj )}(hhh](j )}(hBuilding the TF-A imageh]hBuilding the TF-A image}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAj hCK@ubh block_quote)}(hhh](h literal_block)}(hmake PLAT=arm_fgpa DEBUG=1h]hmake PLAT=arm_fgpa DEBUG=1}(hhh!j ubah"}(h$]h&]h+]h-]h/]forcehighlight_args} xml:spacepreservelanguageshelluh1j hAj hCKBh!j ubj )}(hThis will use the default load addresses as described above. When those addresses need to differ for a certain setup, they can be passed on the make command line:h]hThis will use the default load addresses as described above. When those addresses need to differ for a certain setup, they can be passed on the make command line:}(hj h!j ubah"}(h$]h&]h+]h-]h/]uh1j hAj hCKFh!j ubj )}(hamake PLAT=arm_fgpa DEBUG=1 PRELOADED_BL33_BASE=0x80200000 FPGA_PRELOADED_DTB_BASE=0x80180000 bl31h]hamake PLAT=arm_fgpa DEBUG=1 PRELOADED_BL33_BASE=0x80200000 FPGA_PRELOADED_DTB_BASE=0x80180000 bl31}(hhh!j ubah"}(h$]h&]h+]h-]h/]forcehighlight_args}j j j shelluh1j hAj hCKJh!j ubeh"}(h$]h&]h+]h-]h/]uh1j h!j hhhANhCNubeh"}(h$]building-the-tf-a-imageah&]h+]building the tf-a imageah-]h/]uh1j h!j hhhAj hCK@ubj )}(hhh](j )}(hRunning the TF-A imageh]hRunning the TF-A image}(hj h!j hhhANhCNubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhAj hCKOubj )}(hXYAfter building TF-A, the actual TF-A code will be located in ``bl31.bin`` in the build directory. Additionally there is a ``bl31.axf`` ELF file, which contains BL31, as well as some simple ROM trampoline code (required by the Arm FPGA boot flow) and a generic DTB to support most of the FPGA images. This can be simply handed over to the FPGA payload uploader, which will take care of loading the components at their respective load addresses. In addition to this file you need at least a BL33 payload (typically a Linux kernel image), optionally a Linux initrd image file and possibly a command line:h](h=After building TF-A, the actual TF-A code will be located in }(h=After building TF-A, the actual TF-A code will be located in h!j hhhANhCNubj )}(h ``bl31.bin``h]hbl31.bin}(hhh!j% ubah"}(h$]h&]h+]h-]h/]uh1j h!j ubh1 in the build directory. Additionally there is a }(h1 in the build directory. Additionally there is a h!j hhhANhCNubj )}(h ``bl31.axf``h]hbl31.axf}(hhh!j8 ubah"}(h$]h&]h+]h-]h/]uh1j h!j ubhX ELF file, which contains BL31, as well as some simple ROM trampoline code (required by the Arm FPGA boot flow) and a generic DTB to support most of the FPGA images. This can be simply handed over to the FPGA payload uploader, which will take care of loading the components at their respective load addresses. In addition to this file you need at least a BL33 payload (typically a Linux kernel image), optionally a Linux initrd image file and possibly a command line:}(hX ELF file, which contains BL31, as well as some simple ROM trampoline code (required by the Arm FPGA boot flow) and a generic DTB to support most of the FPGA images. This can be simply handed over to the FPGA payload uploader, which will take care of loading the components at their respective load addresses. In addition to this file you need at least a BL33 payload (typically a Linux kernel image), optionally a Linux initrd image file and possibly a command line:h!j hhhANhCNubeh"}(h$]h&]h+]h-]h/]uh1j hAj hCKQh!j hhubj )}(hhh]j )}(hkfpga-run ... -m bl31.axf -l auto -m Image -l 0x80080000 -m initrd.gz -l 0x84000000 -m cmdline.txt -l 0x1000h]hkfpga-run ... -m bl31.axf -l auto -m Image -l 0x80080000 -m initrd.gz -l 0x84000000 -m cmdline.txt -l 0x1000}(hhh!jT ubah"}(h$]h&]h+]h-]h/]forcehighlight_args}j j j shelluh1j hAj hCK[h!jQ ubah"}(h$]h&]h+]h-]h/]uh1j h!j hhhANhCNubh transition)}(h--------------h]h"}(h$]h&]h+]h-]h/]uh1jl hAj hCK_h!j hhubj )}(h7*Copyright (c) 2020, Arm Limited. All rights reserved.*h]h emphasis)}(hjz h]h5Copyright (c) 2020, Arm Limited. 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