1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip-mpfs-clock.h" 6 7/* Clock frequency (in Hz) of the rtcclk */ 8#define RTCCLK_FREQ 1000000 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 model = "Microchip MPFS Icicle Kit"; 14 compatible = "microchip,mpfs-icicle-kit"; 15 16 aliases { 17 serial0 = &uart0; 18 ethernet0 = &emac1; 19 }; 20 21 chosen { 22 stdout-path = "serial0"; 23 }; 24 25 cpucomplex: cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 timebase-frequency = <RTCCLK_FREQ>; 29 cpu0: cpu@0 { 30 clocks = <&clkcfg CLK_CPU>; 31 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 32 device_type = "cpu"; 33 i-cache-block-size = <64>; 34 i-cache-sets = <128>; 35 i-cache-size = <16384>; 36 reg = <0>; 37 riscv,isa = "rv64imac"; 38 status = "disabled"; 39 operating-points = < 40 /* kHz uV */ 41 600000 1100000 42 300000 950000 43 150000 750000 44 >; 45 cpu0intc: interrupt-controller { 46 #interrupt-cells = <1>; 47 compatible = "riscv,cpu-intc"; 48 interrupt-controller; 49 }; 50 }; 51 cpu1: cpu@1 { 52 clocks = <&clkcfg CLK_CPU>; 53 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 54 d-cache-block-size = <64>; 55 d-cache-sets = <64>; 56 d-cache-size = <32768>; 57 d-tlb-sets = <1>; 58 d-tlb-size = <32>; 59 device_type = "cpu"; 60 i-cache-block-size = <64>; 61 i-cache-sets = <64>; 62 i-cache-size = <32768>; 63 i-tlb-sets = <1>; 64 i-tlb-size = <32>; 65 mmu-type = "riscv,sv39"; 66 reg = <1>; 67 riscv,isa = "rv64imafdc"; 68 tlb-split; 69 status = "okay"; 70 operating-points = < 71 /* kHz uV */ 72 600000 1100000 73 300000 950000 74 150000 750000 75 >; 76 cpu1intc: interrupt-controller { 77 #interrupt-cells = <1>; 78 compatible = "riscv,cpu-intc"; 79 interrupt-controller; 80 }; 81 }; 82 cpu2: cpu@2 { 83 clocks = <&clkcfg CLK_CPU>; 84 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 85 d-cache-block-size = <64>; 86 d-cache-sets = <64>; 87 d-cache-size = <32768>; 88 d-tlb-sets = <1>; 89 d-tlb-size = <32>; 90 device_type = "cpu"; 91 i-cache-block-size = <64>; 92 i-cache-sets = <64>; 93 i-cache-size = <32768>; 94 i-tlb-sets = <1>; 95 i-tlb-size = <32>; 96 mmu-type = "riscv,sv39"; 97 reg = <2>; 98 riscv,isa = "rv64imafdc"; 99 tlb-split; 100 status = "okay"; 101 operating-points = < 102 /* kHz uV */ 103 600000 1100000 104 300000 950000 105 150000 750000 106 >; 107 cpu2intc: interrupt-controller { 108 #interrupt-cells = <1>; 109 compatible = "riscv,cpu-intc"; 110 interrupt-controller; 111 }; 112 }; 113 cpu3: cpu@3 { 114 clocks = <&clkcfg CLK_CPU>; 115 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 116 d-cache-block-size = <64>; 117 d-cache-sets = <64>; 118 d-cache-size = <32768>; 119 d-tlb-sets = <1>; 120 d-tlb-size = <32>; 121 device_type = "cpu"; 122 i-cache-block-size = <64>; 123 i-cache-sets = <64>; 124 i-cache-size = <32768>; 125 i-tlb-sets = <1>; 126 i-tlb-size = <32>; 127 mmu-type = "riscv,sv39"; 128 reg = <3>; 129 riscv,isa = "rv64imafdc"; 130 tlb-split; 131 status = "okay"; 132 operating-points = < 133 /* kHz uV */ 134 600000 1100000 135 300000 950000 136 150000 750000 137 >; 138 cpu3intc: interrupt-controller { 139 #interrupt-cells = <1>; 140 compatible = "riscv,cpu-intc"; 141 interrupt-controller; 142 }; 143 }; 144 cpu4: cpu@4 { 145 clocks = <&clkcfg CLK_CPU>; 146 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 147 d-cache-block-size = <64>; 148 d-cache-sets = <64>; 149 d-cache-size = <32768>; 150 d-tlb-sets = <1>; 151 d-tlb-size = <32>; 152 device_type = "cpu"; 153 i-cache-block-size = <64>; 154 i-cache-sets = <64>; 155 i-cache-size = <32768>; 156 i-tlb-sets = <1>; 157 i-tlb-size = <32>; 158 mmu-type = "riscv,sv39"; 159 reg = <4>; 160 riscv,isa = "rv64imafdc"; 161 tlb-split; 162 status = "okay"; 163 operating-points = < 164 /* kHz uV */ 165 600000 1100000 166 300000 950000 167 150000 750000 168 >; 169 cpu4intc: interrupt-controller { 170 #interrupt-cells = <1>; 171 compatible = "riscv,cpu-intc"; 172 interrupt-controller; 173 }; 174 }; 175 }; 176 refclk: refclk { 177 compatible = "fixed-clock"; 178 #clock-cells = <0>; 179 clock-frequency = <600000000>; 180 clock-output-names = "msspllclk"; 181 }; 182 ddr: memory@80000000 { 183 device_type = "memory"; 184 reg = <0x0 0x80000000 0x0 0x40000000>; 185 clocks = <&clkcfg CLK_DDRC>; 186 }; 187 soc: soc { 188 #address-cells = <2>; 189 #size-cells = <2>; 190 compatible = "microchip,mpfs-icicle-kit", "simple-bus"; 191 ranges; 192 clint0: clint@2000000 { 193 compatible = "riscv,clint0"; 194 interrupts-extended = <&cpu0intc 3 &cpu0intc 7 195 &cpu1intc 3 &cpu1intc 7 196 &cpu2intc 3 &cpu2intc 7 197 &cpu3intc 3 &cpu3intc 7 198 &cpu4intc 3 &cpu4intc 7>; 199 reg = <0x0 0x2000000 0x0 0x10000>; 200 reg-names = "control"; 201 clock-frequency = <RTCCLK_FREQ>; 202 }; 203 cachecontroller: cache-controller@2010000 { 204 compatible = "sifive,fu540-c000-ccache", "cache"; 205 cache-block-size = <64>; 206 cache-level = <2>; 207 cache-sets = <1024>; 208 cache-size = <2097152>; 209 cache-unified; 210 interrupt-parent = <&plic>; 211 interrupts = <1 2 3>; 212 reg = <0x0 0x2010000 0x0 0x1000>; 213 }; 214 plic: interrupt-controller@c000000 { 215 #interrupt-cells = <1>; 216 compatible = "sifive,plic-1.0.0"; 217 reg = <0x0 0xc000000 0x0 0x4000000>; 218 riscv,max-priority = <7>; 219 riscv,ndev = <186>; 220 interrupt-controller; 221 interrupts-extended = < 222 &cpu0intc 11 223 &cpu1intc 11 &cpu1intc 9 224 &cpu2intc 11 &cpu2intc 9 225 &cpu3intc 11 &cpu3intc 9 226 &cpu4intc 11 &cpu4intc 9>; 227 }; 228 uart0: serial@20000000 { 229 compatible = "ns16550a"; 230 reg = <0x0 0x20000000 0x0 0x400>; 231 reg-io-width = <4>; 232 reg-shift = <2>; 233 interrupt-parent = <&plic>; 234 interrupts = <90>; 235 clock-frequency = <150000000>; 236 clocks = <&clkcfg CLK_MMUART0>; 237 status = "okay"; 238 }; 239 clkcfg: clkcfg@20002000 { 240 compatible = "microchip,mpfs-clkcfg"; 241 reg = <0x0 0x20002000 0x0 0x1000>; 242 reg-names = "mss_sysreg"; 243 clocks = <&refclk>; 244 #clock-cells = <1>; 245 clock-output-names = "cpu", "axi", "ahb", "envm", 246 "mac0", "mac1", "mmc", "timer", 247 "mmuart0", "mmuart1", "mmuart2", 248 "mmuart3", "mmuart4", "spi0", "spi1", 249 "i2c0", "i2c1", "can0", "can1", "usb", 250 "reserved", "rtc", "qspi", "gpio0", 251 "gpio1", "gpio2", "ddrc", "fic0", 252 "fic1", "fic2", "fic3", "athena", 253 "cfm"; 254 }; 255 emmc: mmc@20008000 { 256 compatible = "cdns,sd4hc"; 257 reg = <0x0 0x20008000 0x0 0x1000>; 258 interrupt-parent = <&plic>; 259 interrupts = <88 89>; 260 pinctrl-names = "default"; 261 clocks = <&clkcfg CLK_MMC>; 262 bus-width = <4>; 263 cap-mmc-highspeed; 264 mmc-ddr-3_3v; 265 max-frequency = <200000000>; 266 non-removable; 267 no-sd; 268 no-sdio; 269 voltage-ranges = <3300 3300>; 270 status = "okay"; 271 }; 272 sdcard: sd@20008000 { 273 compatible = "cdns,sd4hc"; 274 reg = <0x0 0x20008000 0x0 0x1000>; 275 interrupt-parent = <&plic>; 276 interrupts = <88>; 277 pinctrl-names = "default"; 278 clocks = <&clkcfg CLK_MMC>; 279 bus-width = <4>; 280 disable-wp; 281 cap-sd-highspeed; 282 card-detect-delay = <200>; 283 sd-uhs-sdr12; 284 sd-uhs-sdr25; 285 sd-uhs-sdr50; 286 sd-uhs-sdr104; 287 max-frequency = <200000000>; 288 status = "disabled"; 289 }; 290 uart1: serial@20100000 { 291 compatible = "ns16550a"; 292 reg = <0x0 0x20100000 0x0 0x400>; 293 reg-io-width = <4>; 294 reg-shift = <2>; 295 interrupt-parent = <&plic>; 296 interrupts = <91>; 297 clock-frequency = <150000000>; 298 clocks = <&clkcfg CLK_MMUART1>; 299 status = "okay"; 300 }; 301 uart2: serial@20102000 { 302 compatible = "ns16550a"; 303 reg = <0x0 0x20102000 0x0 0x400>; 304 reg-io-width = <4>; 305 reg-shift = <2>; 306 interrupt-parent = <&plic>; 307 interrupts = <92>; 308 clock-frequency = <150000000>; 309 clocks = <&clkcfg CLK_MMUART2>; 310 status = "okay"; 311 }; 312 uart3: serial@20104000 { 313 compatible = "ns16550a"; 314 reg = <0x0 0x20104000 0x0 0x400>; 315 reg-io-width = <4>; 316 reg-shift = <2>; 317 interrupt-parent = <&plic>; 318 interrupts = <93>; 319 clock-frequency = <150000000>; 320 clocks = <&clkcfg CLK_MMUART3>; 321 status = "okay"; 322 }; 323 i2c0: i2c@2010a000 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 compatible = "microchip,mpfs-mss-i2c"; 327 reg = <0x0 0x2010a000 0x0 0x1000>; 328 interrupt-parent = <&plic>; 329 interrupts = <58>; 330 clocks = <&clkcfg CLK_I2C0>; 331 status = "disabled"; 332 }; 333 i2c1: i2c@2010b000 { 334 #address-cells = <1>; 335 #size-cells = <0>; 336 compatible = "microchip,mpfs-mss-i2c"; 337 reg = <0x0 0x2010b000 0x0 0x1000>; 338 interrupt-parent = <&plic>; 339 interrupts = <61>; 340 clocks = <&clkcfg CLK_I2C1>; 341 status = "disabled"; 342 pac193x@10 { 343 compatible = "microchip,pac1934"; 344 reg = <0x10>; 345 samp-rate = <64>; 346 status = "disabled"; 347 ch1: channel0 { 348 uohms-shunt-res = <10000>; 349 rail-name = "VDD"; 350 channel_enabled; 351 }; 352 ch2: channel1 { 353 uohms-shunt-res = <10000>; 354 rail-name = "VDDA25"; 355 channel_enabled; 356 }; 357 ch3: channel2 { 358 uohms-shunt-res = <10000>; 359 rail-name = "VDD25"; 360 channel_enabled; 361 }; 362 ch4: channel3 { 363 uohms-shunt-res = <10000>; 364 rail-name = "VDDA"; 365 channel_enabled; 366 }; 367 }; 368 }; 369 emac0: ethernet@20110000 { 370 compatible = "microchip,mpfs-mss-gem"; 371 reg = <0x0 0x20110000 0x0 0x2000>; 372 interrupt-parent = <&plic>; 373 interrupts = <64 65 66 67>; 374 local-mac-address = [56 34 00 FC 00 02]; 375 phy-mode = "sgmii"; 376 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>; 377 clock-names = "pclk", "hclk"; 378 status = "disabled"; 379 380 #address-cells = <1>; 381 #size-cells = <0>; 382 phy-handle = <&phy0>; 383 phy0: ethernet-phy@8 { 384 reg = <8>; 385 ti,fifo-depth = <0x01>; 386 }; 387 }; 388 emac1: ethernet@20112000 { 389 compatible = "microchip,mpfs-mss-gem"; 390 reg = <0x0 0x20112000 0x0 0x2000>; 391 interrupt-parent = <&plic>; 392 interrupts = <70 71 72 73>; 393 local-mac-address = [00 00 00 00 00 00]; 394 phy-mode = "sgmii"; 395 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 396 clock-names = "pclk", "hclk"; 397 status = "okay"; 398 399 #address-cells = <1>; 400 #size-cells = <0>; 401 phy-handle = <&phy1>; 402 phy1: ethernet-phy@9 { 403 reg = <9>; 404 ti,fifo-depth = <0x01>; 405 }; 406 }; 407 gpio: gpio@20122000 { 408 compatible = "microchip,mpfs-mss-gpio"; 409 interrupt-parent = <&plic>; 410 interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26 411 27 28 29 30 31 32 33 34 35 36 37 38 39 412 40 41 42 43 44>; 413 gpio-controller; 414 clocks = <&clkcfg CLK_GPIO2>; 415 reg = <0x00 0x20122000 0x0 0x1000>; 416 reg-names = "control"; 417 #gpio-cells = <2>; 418 status = "disabled"; 419 }; 420 }; 421}; 422