1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef TEGRA_PRIVATE_H 9 #define TEGRA_PRIVATE_H 10 11 #include <platform_def.h> 12 #include <stdbool.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/psci/psci.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 20 #include <tegra_gic.h> 21 22 /******************************************************************************* 23 * Implementation defined ACTLR_EL1 bit definitions 24 ******************************************************************************/ 25 #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 26 27 /******************************************************************************* 28 * Implementation defined ACTLR_EL2 bit definitions 29 ******************************************************************************/ 30 #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 31 32 /******************************************************************************* 33 * Struct for parameters received from BL2 34 ******************************************************************************/ 35 typedef struct plat_params_from_bl2 { 36 /* TZ memory size */ 37 uint64_t tzdram_size; 38 /* TZ memory base */ 39 uint64_t tzdram_base; 40 /* UART port ID */ 41 int32_t uart_id; 42 /* L2 ECC parity protection disable flag */ 43 int32_t l2_ecc_parity_prot_dis; 44 /* SHMEM base address for storing the boot logs */ 45 uint64_t boot_profiler_shmem_base; 46 /* System Suspend Entry Firmware size */ 47 uint64_t sc7entry_fw_size; 48 /* System Suspend Entry Firmware base address */ 49 uint64_t sc7entry_fw_base; 50 /* Enable dual execution */ 51 uint8_t enable_ccplex_lock_step; 52 } plat_params_from_bl2_t; 53 54 /******************************************************************************* 55 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 56 ******************************************************************************/ 57 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 58 59 /******************************************************************************* 60 * Struct describing parameters passed to bl31 61 ******************************************************************************/ 62 struct tegra_bl31_params { 63 param_header_t h; 64 image_info_t *bl31_image_info; 65 entry_point_info_t *bl32_ep_info; 66 image_info_t *bl32_image_info; 67 entry_point_info_t *bl33_ep_info; 68 image_info_t *bl33_image_info; 69 }; 70 71 /******************************************************************************* 72 * To suppress Coverity MISRA C-2012 Rule 2.2 violations 73 *******************************************************************************/ 74 #define UNUSED_FUNC_NOP() asm("nop") 75 76 /* Declarations for plat_psci_handlers.c */ 77 int32_t tegra_soc_validate_power_state(uint32_t power_state, 78 psci_power_state_t *req_state); 79 80 /* Declarations for plat_setup.c */ 81 const mmap_region_t *plat_get_mmio_map(void); 82 void plat_enable_console(int32_t id); 83 void plat_gic_setup(void); 84 struct tegra_bl31_params *plat_get_bl31_params(void); 85 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 86 void plat_early_platform_setup(void); 87 void plat_late_platform_setup(void); 88 void plat_relocate_bl32_image(const image_info_t *bl32_img_info); 89 bool plat_supports_system_suspend(void); 90 void plat_runtime_setup(void); 91 92 /* Declarations for plat_secondary.c */ 93 void plat_secondary_setup(void); 94 int32_t plat_lock_cpu_vectors(void); 95 96 /* Declarations for tegra_fiq_glue.c */ 97 void tegra_fiq_handler_setup(void); 98 int32_t tegra_fiq_get_intr_context(void); 99 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 100 101 /* Declarations for tegra_security.c */ 102 void tegra_security_setup(void); 103 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 104 105 /* Declarations for tegra_pm.c */ 106 void tegra_pm_system_suspend_entry(void); 107 void tegra_pm_system_suspend_exit(void); 108 int32_t tegra_system_suspended(void); 109 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state); 110 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 111 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 112 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 113 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 114 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 115 int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state); 116 int32_t tegra_soc_prepare_system_reset(void); 117 __dead2 void tegra_soc_prepare_system_off(void); 118 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 119 const plat_local_state_t *states, 120 uint32_t ncpu); 121 122 /* Declarations for tegraXXX_pm.c */ 123 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 124 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 125 126 /* Declarations for tegra_bl31_setup.c */ 127 plat_params_from_bl2_t *bl31_get_plat_params(void); 128 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 129 130 /* Declarations for tegra_delay_timer.c */ 131 void tegra_delay_timer_init(void); 132 133 void tegra_secure_entrypoint(void); 134 135 /* Declarations for tegra_sip_calls.c */ 136 uintptr_t tegra_sip_handler(uint32_t smc_fid, 137 u_register_t x1, 138 u_register_t x2, 139 u_register_t x3, 140 u_register_t x4, 141 void *cookie, 142 void *handle, 143 u_register_t flags); 144 int plat_sip_handler(uint32_t smc_fid, 145 uint64_t x1, 146 uint64_t x2, 147 uint64_t x3, 148 uint64_t x4, 149 const void *cookie, 150 void *handle, 151 uint64_t flags); 152 153 #if RAS_EXTENSION 154 void tegra194_ras_enable(void); 155 void tegra194_ras_corrected_err_clear(uint64_t *cookie); 156 #endif 157 158 #endif /* TEGRA_PRIVATE_H */ 159