1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2020 Intel Corporation */ 3 #ifndef ADF_GEN2_HW_DATA_H_ 4 #define ADF_GEN2_HW_DATA_H_ 5 6 #include "adf_accel_devices.h" 7 8 /* Transport access */ 9 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL 10 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL 11 #define ADF_RING_CSR_RING_CONFIG 0x000 12 #define ADF_RING_CSR_RING_LBASE 0x040 13 #define ADF_RING_CSR_RING_UBASE 0x080 14 #define ADF_RING_CSR_RING_HEAD 0x0C0 15 #define ADF_RING_CSR_RING_TAIL 0x100 16 #define ADF_RING_CSR_E_STAT 0x14C 17 #define ADF_RING_CSR_INT_FLAG 0x170 18 #define ADF_RING_CSR_INT_SRCSEL 0x174 19 #define ADF_RING_CSR_INT_SRCSEL_2 0x178 20 #define ADF_RING_CSR_INT_COL_EN 0x17C 21 #define ADF_RING_CSR_INT_COL_CTL 0x180 22 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 23 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 24 #define ADF_RING_BUNDLE_SIZE 0x1000 25 #define ADF_GEN2_RX_RINGS_OFFSET 8 26 #define ADF_GEN2_TX_RINGS_MASK 0xFF 27 28 #define BUILD_RING_BASE_ADDR(addr, size) \ 29 (((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) 30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 32 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 35 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 38 ADF_RING_CSR_E_STAT) 39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 41 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value) 42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 43 do { \ 44 u32 l_base = 0, u_base = 0; \ 45 l_base = (u32)((value) & 0xFFFFFFFF); \ 46 u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \ 47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 48 ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \ 49 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 50 ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \ 51 } while (0) 52 53 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 54 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 55 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value) 56 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 57 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 58 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value) 59 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 60 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 61 ADF_RING_CSR_INT_FLAG, value) 62 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 63 do { \ 64 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 65 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \ 66 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 67 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \ 68 } while (0) 69 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 70 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 71 ADF_RING_CSR_INT_COL_EN, value) 72 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 73 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 74 ADF_RING_CSR_INT_COL_CTL, \ 75 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 76 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 77 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 78 ADF_RING_CSR_INT_FLAG_AND_COL, value) 79 80 /* AE to function map */ 81 #define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190) 82 #define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310) 83 #define AE2FUNCTION_MAP_REG_SIZE 4 84 #define AE2FUNCTION_MAP_VALID BIT(7) 85 86 #define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \ 87 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \ 88 AE2FUNCTION_MAP_REG_SIZE * (index)) 89 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \ 90 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \ 91 AE2FUNCTION_MAP_REG_SIZE * (index), value) 92 #define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \ 93 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \ 94 AE2FUNCTION_MAP_REG_SIZE * (index)) 95 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \ 96 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \ 97 AE2FUNCTION_MAP_REG_SIZE * (index), value) 98 99 /* Admin Interface Offsets */ 100 #define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 101 #define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 102 #define ADF_MAILBOX_BASE_OFFSET 0x20970 103 104 /* Arbiter configuration */ 105 #define ADF_ARB_OFFSET 0x30000 106 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180 107 #define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0)) 108 #define ADF_ARB_REG_SLOT 0x1000 109 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C 110 111 #define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \ 112 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \ 113 (ADF_ARB_REG_SLOT * (index)), value) 114 115 /* Power gating */ 116 #define ADF_POWERGATE_PKE BIT(24) 117 118 /* WDT timers 119 * 120 * Timeout is in cycles. Clock speed may vary across products but this 121 * value should be a few milli-seconds. 122 */ 123 #define ADF_SSM_WDT_DEFAULT_VALUE 0x200000 124 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x2000000 125 #define ADF_SSMWDT_OFFSET 0x54 126 #define ADF_SSMWDTPKE_OFFSET 0x58 127 #define ADF_SSMWDT(i) (ADF_SSMWDT_OFFSET + ((i) * 0x4000)) 128 #define ADF_SSMWDTPKE(i) (ADF_SSMWDTPKE_OFFSET + ((i) * 0x4000)) 129 130 /* Error detection and correction */ 131 #define ADF_GEN2_AE_CTX_ENABLES(i) ((i) * 0x1000 + 0x20818) 132 #define ADF_GEN2_AE_MISC_CONTROL(i) ((i) * 0x1000 + 0x20960) 133 #define ADF_GEN2_ENABLE_AE_ECC_ERR BIT(28) 134 #define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 135 #define ADF_GEN2_UERRSSMSH(i) ((i) * 0x4000 + 0x18) 136 #define ADF_GEN2_CERRSSMSH(i) ((i) * 0x4000 + 0x10) 137 #define ADF_GEN2_ERRSSMSH_EN BIT(3) 138 139 /* VF2PF interrupts */ 140 #define ADF_GEN2_ERRSOU3 (0x3A000 + 0x0C) 141 #define ADF_GEN2_ERRSOU5 (0x3A000 + 0xD8) 142 #define ADF_GEN2_ERRMSK3 (0x3A000 + 0x1C) 143 #define ADF_GEN2_ERRMSK5 (0x3A000 + 0xDC) 144 #define ADF_GEN2_ERR_REG_VF2PF(vf_src) (((vf_src) & 0x01FFFE00) >> 9) 145 #define ADF_GEN2_ERR_MSK_VF2PF(vf_mask) (((vf_mask) & 0xFFFF) << 9) 146 147 u32 adf_gen2_get_pf2vf_offset(u32 i); 148 u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_bar); 149 void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask); 150 void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask); 151 152 u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self); 153 u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self); 154 void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev); 155 void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable, 156 int num_a_regs, int num_b_regs); 157 void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops); 158 void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info); 159 void adf_gen2_get_arb_info(struct arb_info *arb_info); 160 u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev); 161 void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 162 163 #endif 164