1 /*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26
27 #include "drm.h"
28
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32
33 /**
34 * DOC: overview
35 *
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
40 *
41 * Format Modifiers
42 * ----------------
43 *
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
48 *
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
53 *
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
60 *
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
63 * another modifier. For instance, it's incorrect to encode pitch alignment in
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
65 * aligned modifier. That said, modifiers can have implicit minimal
66 * requirements.
67 *
68 * For modifiers where the combination of fourcc code and modifier can alias,
69 * a canonical pair needs to be defined and used by all drivers. Preferred
70 * combinations are also encouraged where all combinations might lead to
71 * confusion and unnecessarily reduced interoperability. An example for the
72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
73 *
74 * There are two kinds of modifier users:
75 *
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
77 * don't alias, otherwise two drivers might support the same format but use
78 * different aliases, preventing them from sharing buffers in an efficient
79 * format.
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81 * see modifiers as opaque tokens they can check for equality and intersect.
82 * These users musn't need to know to reason about the modifier value
83 * (i.e. they are not expected to extract information out of the modifier).
84 *
85 * Vendors should document their modifier usage in as much detail as
86 * possible, to ensure maximum compatibility across devices, drivers and
87 * applications.
88 *
89 * The authoritative list of format modifier codes is found in
90 * `include/uapi/drm/drm_fourcc.h`
91 */
92
93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
94 ((__u32)(c) << 16) | ((__u32)(d) << 24))
95
96 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
97
98 /* Reserve 0 for the invalid format specifier */
99 #define DRM_FORMAT_INVALID 0
100
101 /* color index */
102 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
103
104 /* 8 bpp Red */
105 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
106
107 /* 10 bpp Red */
108 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
109
110 /* 12 bpp Red */
111 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
112
113 /* 16 bpp Red */
114 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
115
116 /* 16 bpp RG */
117 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
118 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
119
120 /* 32 bpp RG */
121 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
122 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
123
124 /* 8 bpp RGB */
125 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
126 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
127
128 /* 16 bpp RGB */
129 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
130 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
131 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
132 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
133
134 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
135 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
136 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
137 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
138
139 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
140 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
141 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
142 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
143
144 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
145 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
146 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
147 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
148
149 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
150 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
151
152 /* 24 bpp RGB */
153 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
154 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
155
156 /* 32 bpp RGB */
157 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
158 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
159 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
160 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
161
162 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
163 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
164 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
165 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
166
167 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
168 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
169 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
170 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
171
172 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
173 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
174 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
175 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
176
177 /* 64 bpp RGB */
178 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
179 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
180
181 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
182 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
183
184 /*
185 * Floating point 64bpp RGB
186 * IEEE 754-2008 binary16 half-precision float
187 * [15:0] sign:exponent:mantissa 1:5:10
188 */
189 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
190 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
191
192 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
193 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
194
195 /*
196 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
197 * of unused padding per component:
198 */
199 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
200
201 /* packed YCbCr */
202 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
203 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
204 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
205 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
206
207 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
208 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
209 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
210 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
211
212 /*
213 * packed Y2xx indicate for each component, xx valid data occupy msb
214 * 16-xx padding occupy lsb
215 */
216 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
217 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
218 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
219
220 /*
221 * packed Y4xx indicate for each component, xx valid data occupy msb
222 * 16-xx padding occupy lsb except Y410
223 */
224 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
225 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
226 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
227
228 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
229 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
230 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
231
232 /*
233 * packed YCbCr420 2x2 tiled formats
234 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
235 */
236 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
237 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
238 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
239 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
240
241 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
242 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
243 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
244 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
245
246 /*
247 * 1-plane YUV 4:2:0
248 * In these formats, the component ordering is specified (Y, followed by U
249 * then V), but the exact Linear layout is undefined.
250 * These formats can only be used with a non-Linear modifier.
251 */
252 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
253 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
254
255 /*
256 * 2 plane RGB + A
257 * index 0 = RGB plane, same format as the corresponding non _A8 format has
258 * index 1 = A plane, [7:0] A
259 */
260 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
261 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
262 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
263 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
264 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
265 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
266 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
267 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
268
269 /*
270 * 2 plane YCbCr
271 * index 0 = Y plane, [7:0] Y
272 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
273 * or
274 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
275 */
276 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
277 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
278 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
279 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
280 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
281 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
282 /*
283 * 2 plane YCbCr
284 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
285 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
286 */
287 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
288
289 /*
290 * 2 plane YCbCr MSB aligned
291 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
292 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
293 */
294 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
295
296 /*
297 * 2 plane YCbCr MSB aligned
298 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
299 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
300 */
301 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
302
303 /*
304 * 2 plane YCbCr MSB aligned
305 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
306 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
307 */
308 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
309
310 /*
311 * 2 plane YCbCr MSB aligned
312 * index 0 = Y plane, [15:0] Y little endian
313 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
314 */
315 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
316
317 /* 3 plane non-subsampled (444) YCbCr
318 * 16 bits per component, but only 10 bits are used and 6 bits are padded
319 * index 0: Y plane, [15:0] Y:x [10:6] little endian
320 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
321 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
322 */
323 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
324
325 /* 3 plane non-subsampled (444) YCrCb
326 * 16 bits per component, but only 10 bits are used and 6 bits are padded
327 * index 0: Y plane, [15:0] Y:x [10:6] little endian
328 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
329 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
330 */
331 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
332
333 /*
334 * 3 plane YCbCr
335 * index 0: Y plane, [7:0] Y
336 * index 1: Cb plane, [7:0] Cb
337 * index 2: Cr plane, [7:0] Cr
338 * or
339 * index 1: Cr plane, [7:0] Cr
340 * index 2: Cb plane, [7:0] Cb
341 */
342 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
343 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
344 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
345 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
346 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
347 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
348 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
349 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
350 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
351 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
352
353
354 /*
355 * Format Modifiers:
356 *
357 * Format modifiers describe, typically, a re-ordering or modification
358 * of the data in a plane of an FB. This can be used to express tiled/
359 * swizzled formats, or compression, or a combination of the two.
360 *
361 * The upper 8 bits of the format modifier are a vendor-id as assigned
362 * below. The lower 56 bits are assigned as vendor sees fit.
363 */
364
365 /* Vendor Ids: */
366 #define DRM_FORMAT_MOD_VENDOR_NONE 0
367 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
368 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
369 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
370 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
371 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
372 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
373 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
374 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
375 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
376 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
377
378 /* add more to the end as needed */
379
380 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
381
382 #define fourcc_mod_get_vendor(modifier) \
383 (((modifier) >> 56) & 0xff)
384
385 #define fourcc_mod_is_vendor(modifier, vendor) \
386 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
387
388 #define fourcc_mod_code(vendor, val) \
389 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
390
391 /*
392 * Format Modifier tokens:
393 *
394 * When adding a new token please document the layout with a code comment,
395 * similar to the fourcc codes above. drm_fourcc.h is considered the
396 * authoritative source for all of these.
397 *
398 * Generic modifier names:
399 *
400 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
401 * for layouts which are common across multiple vendors. To preserve
402 * compatibility, in cases where a vendor-specific definition already exists and
403 * a generic name for it is desired, the common name is a purely symbolic alias
404 * and must use the same numerical value as the original definition.
405 *
406 * Note that generic names should only be used for modifiers which describe
407 * generic layouts (such as pixel re-ordering), which may have
408 * independently-developed support across multiple vendors.
409 *
410 * In future cases where a generic layout is identified before merging with a
411 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
412 * 'NONE' could be considered. This should only be for obvious, exceptional
413 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
414 * apply to a single vendor.
415 *
416 * Generic names should not be used for cases where multiple hardware vendors
417 * have implementations of the same standardised compression scheme (such as
418 * AFBC). In those cases, all implementations should use the same format
419 * modifier(s), reflecting the vendor of the standard.
420 */
421
422 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
423
424 /*
425 * Invalid Modifier
426 *
427 * This modifier can be used as a sentinel to terminate the format modifiers
428 * list, or to initialize a variable with an invalid modifier. It might also be
429 * used to report an error back to userspace for certain APIs.
430 */
431 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
432
433 /*
434 * Linear Layout
435 *
436 * Just plain linear layout. Note that this is different from no specifying any
437 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
438 * which tells the driver to also take driver-internal information into account
439 * and so might actually result in a tiled framebuffer.
440 */
441 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
442
443 /*
444 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
445 *
446 * The "none" format modifier doesn't actually mean that the modifier is
447 * implicit, instead it means that the layout is linear. Whether modifiers are
448 * used is out-of-band information carried in an API-specific way (e.g. in a
449 * flag for drm_mode_fb_cmd2).
450 */
451 #define DRM_FORMAT_MOD_NONE 0
452
453 /* Intel framebuffer modifiers */
454
455 /*
456 * Intel X-tiling layout
457 *
458 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
459 * in row-major layout. Within the tile bytes are laid out row-major, with
460 * a platform-dependent stride. On top of that the memory can apply
461 * platform-depending swizzling of some higher address bits into bit6.
462 *
463 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
464 * On earlier platforms the is highly platforms specific and not useful for
465 * cross-driver sharing. It exists since on a given platform it does uniquely
466 * identify the layout in a simple way for i915-specific userspace, which
467 * facilitated conversion of userspace to modifiers. Additionally the exact
468 * format on some really old platforms is not known.
469 */
470 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
471
472 /*
473 * Intel Y-tiling layout
474 *
475 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
476 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
477 * chunks column-major, with a platform-dependent height. On top of that the
478 * memory can apply platform-depending swizzling of some higher address bits
479 * into bit6.
480 *
481 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
482 * On earlier platforms the is highly platforms specific and not useful for
483 * cross-driver sharing. It exists since on a given platform it does uniquely
484 * identify the layout in a simple way for i915-specific userspace, which
485 * facilitated conversion of userspace to modifiers. Additionally the exact
486 * format on some really old platforms is not known.
487 */
488 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
489
490 /*
491 * Intel Yf-tiling layout
492 *
493 * This is a tiled layout using 4Kb tiles in row-major layout.
494 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
495 * are arranged in four groups (two wide, two high) with column-major layout.
496 * Each group therefore consits out of four 256 byte units, which are also laid
497 * out as 2x2 column-major.
498 * 256 byte units are made out of four 64 byte blocks of pixels, producing
499 * either a square block or a 2:1 unit.
500 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
501 * in pixel depends on the pixel depth.
502 */
503 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
504
505 /*
506 * Intel color control surface (CCS) for render compression
507 *
508 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
509 * The main surface will be plane index 0 and must be Y/Yf-tiled,
510 * the CCS will be plane index 1.
511 *
512 * Each CCS tile matches a 1024x512 pixel area of the main surface.
513 * To match certain aspects of the 3D hardware the CCS is
514 * considered to be made up of normal 128Bx32 Y tiles, Thus
515 * the CCS pitch must be specified in multiples of 128 bytes.
516 *
517 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
518 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
519 * But that fact is not relevant unless the memory is accessed
520 * directly.
521 */
522 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
523 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
524
525 /*
526 * Intel color control surfaces (CCS) for Gen-12 render compression.
527 *
528 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
529 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
530 * main surface. In other words, 4 bits in CCS map to a main surface cache
531 * line pair. The main surface pitch is required to be a multiple of four
532 * Y-tile widths.
533 */
534 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
535
536 /*
537 * Intel color control surfaces (CCS) for Gen-12 media compression
538 *
539 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
540 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
541 * main surface. In other words, 4 bits in CCS map to a main surface cache
542 * line pair. The main surface pitch is required to be a multiple of four
543 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
544 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
545 * planes 2 and 3 for the respective CCS.
546 */
547 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
548
549 /*
550 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
551 * compression.
552 *
553 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
554 * and at index 1. The clear color is stored at index 2, and the pitch should
555 * be ignored. The clear color structure is 256 bits. The first 128 bits
556 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
557 * by 32 bits. The raw clear color is consumed by the 3d engine and generates
558 * the converted clear color of size 64 bits. The first 32 bits store the Lower
559 * Converted Clear Color value and the next 32 bits store the Higher Converted
560 * Clear Color value when applicable. The Converted Clear Color values are
561 * consumed by the DE. The last 64 bits are used to store Color Discard Enable
562 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
563 * corresponds to an area of 4x1 tiles in the main surface. The main surface
564 * pitch is required to be a multiple of 4 tile widths.
565 */
566 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
567
568 /*
569 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
570 *
571 * Macroblocks are laid in a Z-shape, and each pixel data is following the
572 * standard NV12 style.
573 * As for NV12, an image is the result of two frame buffers: one for Y,
574 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
575 * Alignment requirements are (for each buffer):
576 * - multiple of 128 pixels for the width
577 * - multiple of 32 pixels for the height
578 *
579 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
580 */
581 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
582
583 /*
584 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
585 *
586 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
587 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
588 * they correspond to their 16x16 luma block.
589 */
590 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
591
592 /*
593 * Qualcomm Compressed Format
594 *
595 * Refers to a compressed variant of the base format that is compressed.
596 * Implementation may be platform and base-format specific.
597 *
598 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
599 * Pixel data pitch/stride is aligned with macrotile width.
600 * Pixel data height is aligned with macrotile height.
601 * Entire pixel data buffer is aligned with 4k(bytes).
602 */
603 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
604
605 /* Vivante framebuffer modifiers */
606
607 /*
608 * Vivante 4x4 tiling layout
609 *
610 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
611 * layout.
612 */
613 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
614
615 /*
616 * Vivante 64x64 super-tiling layout
617 *
618 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
619 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
620 * major layout.
621 *
622 * For more information: see
623 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
624 */
625 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
626
627 /*
628 * Vivante 4x4 tiling layout for dual-pipe
629 *
630 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
631 * different base address. Offsets from the base addresses are therefore halved
632 * compared to the non-split tiled layout.
633 */
634 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
635
636 /*
637 * Vivante 64x64 super-tiling layout for dual-pipe
638 *
639 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
640 * starts at a different base address. Offsets from the base addresses are
641 * therefore halved compared to the non-split super-tiled layout.
642 */
643 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
644
645 /* NVIDIA frame buffer modifiers */
646
647 /*
648 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
649 *
650 * Pixels are arranged in simple tiles of 16 x 16 bytes.
651 */
652 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
653
654 /*
655 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
656 * and Tegra GPUs starting with Tegra K1.
657 *
658 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
659 * based on the architecture generation. GOBs themselves are then arranged in
660 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
661 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
662 * a block depth or height of "4").
663 *
664 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
665 * in full detail.
666 *
667 * Macro
668 * Bits Param Description
669 * ---- ----- -----------------------------------------------------------------
670 *
671 * 3:0 h log2(height) of each block, in GOBs. Placed here for
672 * compatibility with the existing
673 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
674 *
675 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
676 * compatibility with the existing
677 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
678 *
679 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
680 * size). Must be zero.
681 *
682 * Note there is no log2(width) parameter. Some portions of the
683 * hardware support a block width of two gobs, but it is impractical
684 * to use due to lack of support elsewhere, and has no known
685 * benefits.
686 *
687 * 11:9 - Reserved (To support 2D-array textures with variable array stride
688 * in blocks, specified via log2(tile width in blocks)). Must be
689 * zero.
690 *
691 * 19:12 k Page Kind. This value directly maps to a field in the page
692 * tables of all GPUs >= NV50. It affects the exact layout of bits
693 * in memory and can be derived from the tuple
694 *
695 * (format, GPU model, compression type, samples per pixel)
696 *
697 * Where compression type is defined below. If GPU model were
698 * implied by the format modifier, format, or memory buffer, page
699 * kind would not need to be included in the modifier itself, but
700 * since the modifier should define the layout of the associated
701 * memory buffer independent from any device or other context, it
702 * must be included here.
703 *
704 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
705 * starting with Fermi GPUs. Additionally, the mapping between page
706 * kind and bit layout has changed at various points.
707 *
708 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
709 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
710 * 2 = Gob Height 8, Turing+ Page Kind mapping
711 * 3 = Reserved for future use.
712 *
713 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
714 * bit remapping step that occurs at an even lower level than the
715 * page kind and block linear swizzles. This causes the layout of
716 * surfaces mapped in those SOC's GPUs to be incompatible with the
717 * equivalent mapping on other GPUs in the same system.
718 *
719 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
720 * 1 = Desktop GPU and Tegra Xavier+ Layout
721 *
722 * 25:23 c Lossless Framebuffer Compression type.
723 *
724 * 0 = none
725 * 1 = ROP/3D, layout 1, exact compression format implied by Page
726 * Kind field
727 * 2 = ROP/3D, layout 2, exact compression format implied by Page
728 * Kind field
729 * 3 = CDE horizontal
730 * 4 = CDE vertical
731 * 5 = Reserved for future use
732 * 6 = Reserved for future use
733 * 7 = Reserved for future use
734 *
735 * 55:25 - Reserved for future use. Must be zero.
736 */
737 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
738 fourcc_mod_code(NVIDIA, (0x10 | \
739 ((h) & 0xf) | \
740 (((k) & 0xff) << 12) | \
741 (((g) & 0x3) << 20) | \
742 (((s) & 0x1) << 22) | \
743 (((c) & 0x7) << 23)))
744
745 /* To grandfather in prior block linear format modifiers to the above layout,
746 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
747 * with block-linear layouts, is remapped within drivers to the value 0xfe,
748 * which corresponds to the "generic" kind used for simple single-sample
749 * uncompressed color formats on Fermi - Volta GPUs.
750 */
751 static inline __u64
drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)752 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
753 {
754 if (!(modifier & 0x10) || (modifier & (0xff << 12)))
755 return modifier;
756 else
757 return modifier | (0xfe << 12);
758 }
759
760 /*
761 * 16Bx2 Block Linear layout, used by Tegra K1 and later
762 *
763 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
764 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
765 *
766 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
767 *
768 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
769 * Valid values are:
770 *
771 * 0 == ONE_GOB
772 * 1 == TWO_GOBS
773 * 2 == FOUR_GOBS
774 * 3 == EIGHT_GOBS
775 * 4 == SIXTEEN_GOBS
776 * 5 == THIRTYTWO_GOBS
777 *
778 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
779 * in full detail.
780 */
781 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
782 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
783
784 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
785 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
786 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
787 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
788 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
789 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
790 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
791 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
792 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
793 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
794 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
795 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
796
797 /*
798 * Some Broadcom modifiers take parameters, for example the number of
799 * vertical lines in the image. Reserve the lower 32 bits for modifier
800 * type, and the next 24 bits for parameters. Top 8 bits are the
801 * vendor code.
802 */
803 #define __fourcc_mod_broadcom_param_shift 8
804 #define __fourcc_mod_broadcom_param_bits 48
805 #define fourcc_mod_broadcom_code(val, params) \
806 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
807 #define fourcc_mod_broadcom_param(m) \
808 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
809 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
810 #define fourcc_mod_broadcom_mod(m) \
811 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
812 __fourcc_mod_broadcom_param_shift))
813
814 /*
815 * Broadcom VC4 "T" format
816 *
817 * This is the primary layout that the V3D GPU can texture from (it
818 * can't do linear). The T format has:
819 *
820 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
821 * pixels at 32 bit depth.
822 *
823 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
824 * 16x16 pixels).
825 *
826 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
827 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
828 * they're (TR, BR, BL, TL), where bottom left is start of memory.
829 *
830 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
831 * tiles) or right-to-left (odd rows of 4k tiles).
832 */
833 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
834
835 /*
836 * Broadcom SAND format
837 *
838 * This is the native format that the H.264 codec block uses. For VC4
839 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
840 *
841 * The image can be considered to be split into columns, and the
842 * columns are placed consecutively into memory. The width of those
843 * columns can be either 32, 64, 128, or 256 pixels, but in practice
844 * only 128 pixel columns are used.
845 *
846 * The pitch between the start of each column is set to optimally
847 * switch between SDRAM banks. This is passed as the number of lines
848 * of column width in the modifier (we can't use the stride value due
849 * to various core checks that look at it , so you should set the
850 * stride to width*cpp).
851 *
852 * Note that the column height for this format modifier is the same
853 * for all of the planes, assuming that each column contains both Y
854 * and UV. Some SAND-using hardware stores UV in a separate tiled
855 * image from Y to reduce the column height, which is not supported
856 * with these modifiers.
857 */
858
859 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
860 fourcc_mod_broadcom_code(2, v)
861 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
862 fourcc_mod_broadcom_code(3, v)
863 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
864 fourcc_mod_broadcom_code(4, v)
865 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
866 fourcc_mod_broadcom_code(5, v)
867
868 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
869 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
870 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
871 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
872 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
873 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
874 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
875 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
876
877 /* Broadcom UIF format
878 *
879 * This is the common format for the current Broadcom multimedia
880 * blocks, including V3D 3.x and newer, newer video codecs, and
881 * displays.
882 *
883 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
884 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
885 * stored in columns, with padding between the columns to ensure that
886 * moving from one column to the next doesn't hit the same SDRAM page
887 * bank.
888 *
889 * To calculate the padding, it is assumed that each hardware block
890 * and the software driving it knows the platform's SDRAM page size,
891 * number of banks, and XOR address, and that it's identical between
892 * all blocks using the format. This tiling modifier will use XOR as
893 * necessary to reduce the padding. If a hardware block can't do XOR,
894 * the assumption is that a no-XOR tiling modifier will be created.
895 */
896 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
897
898 /*
899 * Arm Framebuffer Compression (AFBC) modifiers
900 *
901 * AFBC is a proprietary lossless image compression protocol and format.
902 * It provides fine-grained random access and minimizes the amount of data
903 * transferred between IP blocks.
904 *
905 * AFBC has several features which may be supported and/or used, which are
906 * represented using bits in the modifier. Not all combinations are valid,
907 * and different devices or use-cases may support different combinations.
908 *
909 * Further information on the use of AFBC modifiers can be found in
910 * Documentation/gpu/afbc.rst
911 */
912
913 /*
914 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
915 * modifiers) denote the category for modifiers. Currently we have three
916 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
917 * sixteen different categories.
918 */
919 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
920 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
921
922 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
923 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
924
925 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
926 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
927
928 /*
929 * AFBC superblock size
930 *
931 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
932 * size (in pixels) must be aligned to a multiple of the superblock size.
933 * Four lowest significant bits(LSBs) are reserved for block size.
934 *
935 * Where one superblock size is specified, it applies to all planes of the
936 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
937 * the first applies to the Luma plane and the second applies to the Chroma
938 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
939 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
940 */
941 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
942 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
943 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
944 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
945 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
946
947 /*
948 * AFBC lossless colorspace transform
949 *
950 * Indicates that the buffer makes use of the AFBC lossless colorspace
951 * transform.
952 */
953 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
954
955 /*
956 * AFBC block-split
957 *
958 * Indicates that the payload of each superblock is split. The second
959 * half of the payload is positioned at a predefined offset from the start
960 * of the superblock payload.
961 */
962 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
963
964 /*
965 * AFBC sparse layout
966 *
967 * This flag indicates that the payload of each superblock must be stored at a
968 * predefined position relative to the other superblocks in the same AFBC
969 * buffer. This order is the same order used by the header buffer. In this mode
970 * each superblock is given the same amount of space as an uncompressed
971 * superblock of the particular format would require, rounding up to the next
972 * multiple of 128 bytes in size.
973 */
974 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
975
976 /*
977 * AFBC copy-block restrict
978 *
979 * Buffers with this flag must obey the copy-block restriction. The restriction
980 * is such that there are no copy-blocks referring across the border of 8x8
981 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
982 */
983 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
984
985 /*
986 * AFBC tiled layout
987 *
988 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
989 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
990 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
991 * larger bpp formats. The order between the tiles is scan line.
992 * When the tiled layout is used, the buffer size (in pixels) must be aligned
993 * to the tile size.
994 */
995 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
996
997 /*
998 * AFBC solid color blocks
999 *
1000 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1001 * can be reduced if a whole superblock is a single color.
1002 */
1003 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
1004
1005 /*
1006 * AFBC double-buffer
1007 *
1008 * Indicates that the buffer is allocated in a layout safe for front-buffer
1009 * rendering.
1010 */
1011 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1012
1013 /*
1014 * AFBC buffer content hints
1015 *
1016 * Indicates that the buffer includes per-superblock content hints.
1017 */
1018 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1019
1020 /* AFBC uncompressed storage mode
1021 *
1022 * Indicates that the buffer is using AFBC uncompressed storage mode.
1023 * In this mode all superblock payloads in the buffer use the uncompressed
1024 * storage mode, which is usually only used for data which cannot be compressed.
1025 * The buffer layout is the same as for AFBC buffers without USM set, this only
1026 * affects the storage mode of the individual superblocks. Note that even a
1027 * buffer without USM set may use uncompressed storage mode for some or all
1028 * superblocks, USM just guarantees it for all.
1029 */
1030 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1031
1032 /*
1033 * Arm Fixed-Rate Compression (AFRC) modifiers
1034 *
1035 * AFRC is a proprietary fixed rate image compression protocol and format,
1036 * designed to provide guaranteed bandwidth and memory footprint
1037 * reductions in graphics and media use-cases.
1038 *
1039 * AFRC buffers consist of one or more planes, with the same components
1040 * and meaning as an uncompressed buffer using the same pixel format.
1041 *
1042 * Within each plane, the pixel/luma/chroma values are grouped into
1043 * "coding unit" blocks which are individually compressed to a
1044 * fixed size (in bytes). All coding units within a given plane of a buffer
1045 * store the same number of values, and have the same compressed size.
1046 *
1047 * The coding unit size is configurable, allowing different rates of compression.
1048 *
1049 * The start of each AFRC buffer plane must be aligned to an alignment granule which
1050 * depends on the coding unit size.
1051 *
1052 * Coding Unit Size Plane Alignment
1053 * ---------------- ---------------
1054 * 16 bytes 1024 bytes
1055 * 24 bytes 512 bytes
1056 * 32 bytes 2048 bytes
1057 *
1058 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
1059 * to a multiple of the paging tile dimensions.
1060 * The dimensions of each paging tile depend on whether the buffer is optimised for
1061 * scanline (SCAN layout) or rotated (ROT layout) access.
1062 *
1063 * Layout Paging Tile Width Paging Tile Height
1064 * ------ ----------------- ------------------
1065 * SCAN 16 coding units 4 coding units
1066 * ROT 8 coding units 8 coding units
1067 *
1068 * The dimensions of each coding unit depend on the number of components
1069 * in the compressed plane and whether the buffer is optimised for
1070 * scanline (SCAN layout) or rotated (ROT layout) access.
1071 *
1072 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
1073 * ----------------------------- --------- ----------------- ------------------
1074 * 1 SCAN 16 samples 4 samples
1075 * Example: 16x4 luma samples in a 'Y' plane
1076 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1077 * ----------------------------- --------- ----------------- ------------------
1078 * 1 ROT 8 samples 8 samples
1079 * Example: 8x8 luma samples in a 'Y' plane
1080 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1081 * ----------------------------- --------- ----------------- ------------------
1082 * 2 DONT CARE 8 samples 4 samples
1083 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1084 * ----------------------------- --------- ----------------- ------------------
1085 * 3 DONT CARE 4 samples 4 samples
1086 * Example: 4x4 pixels in an RGB buffer without alpha
1087 * ----------------------------- --------- ----------------- ------------------
1088 * 4 DONT CARE 4 samples 4 samples
1089 * Example: 4x4 pixels in an RGB buffer with alpha
1090 */
1091
1092 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
1093
1094 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
1095 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
1096
1097 /*
1098 * AFRC coding unit size modifier.
1099 *
1100 * Indicates the number of bytes used to store each compressed coding unit for
1101 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
1102 * is the same for both Cb and Cr, which may be stored in separate planes.
1103 *
1104 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
1105 * each compressed coding unit in the first plane of the buffer. For RGBA buffers
1106 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1107 * this corresponds to the luma plane.
1108 *
1109 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
1110 * each compressed coding unit in the second and third planes in the buffer.
1111 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1112 *
1113 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1114 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
1115 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1116 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
1117 */
1118 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
1119 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1120 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
1121 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
1122
1123 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
1124 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
1125
1126 /*
1127 * AFRC scanline memory layout.
1128 *
1129 * Indicates if the buffer uses the scanline-optimised layout
1130 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1131 * The memory layout is the same for all planes.
1132 */
1133 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1134
1135 /*
1136 * Arm 16x16 Block U-Interleaved modifier
1137 *
1138 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1139 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1140 * in the block are reordered.
1141 */
1142 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1143 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1144
1145 /*
1146 * Allwinner tiled modifier
1147 *
1148 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1149 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1150 * planes.
1151 *
1152 * With this tiling, the luminance samples are disposed in tiles representing
1153 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1154 * The pixel order in each tile is linear and the tiles are disposed linearly,
1155 * both in row-major order.
1156 */
1157 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1158
1159 /*
1160 * Amlogic Video Framebuffer Compression modifiers
1161 *
1162 * Amlogic uses a proprietary lossless image compression protocol and format
1163 * for their hardware video codec accelerators, either video decoders or
1164 * video input encoders.
1165 *
1166 * It considerably reduces memory bandwidth while writing and reading
1167 * frames in memory.
1168 *
1169 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1170 * per component YCbCr 420, single plane :
1171 * - DRM_FORMAT_YUV420_8BIT
1172 * - DRM_FORMAT_YUV420_10BIT
1173 *
1174 * The first 8 bits of the mode defines the layout, then the following 8 bits
1175 * defines the options changing the layout.
1176 *
1177 * Not all combinations are valid, and different SoCs may support different
1178 * combinations of layout and options.
1179 */
1180 #define __fourcc_mod_amlogic_layout_mask 0xff
1181 #define __fourcc_mod_amlogic_options_shift 8
1182 #define __fourcc_mod_amlogic_options_mask 0xff
1183
1184 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1185 fourcc_mod_code(AMLOGIC, \
1186 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1187 (((__options) & __fourcc_mod_amlogic_options_mask) \
1188 << __fourcc_mod_amlogic_options_shift))
1189
1190 /* Amlogic FBC Layouts */
1191
1192 /*
1193 * Amlogic FBC Basic Layout
1194 *
1195 * The basic layout is composed of:
1196 * - a body content organized in 64x32 superblocks with 4096 bytes per
1197 * superblock in default mode.
1198 * - a 32 bytes per 128x64 header block
1199 *
1200 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1201 */
1202 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1203
1204 /*
1205 * Amlogic FBC Scatter Memory layout
1206 *
1207 * Indicates the header contains IOMMU references to the compressed
1208 * frames content to optimize memory access and layout.
1209 *
1210 * In this mode, only the header memory address is needed, thus the
1211 * content memory organization is tied to the current producer
1212 * execution and cannot be saved/dumped neither transferrable between
1213 * Amlogic SoCs supporting this modifier.
1214 *
1215 * Due to the nature of the layout, these buffers are not expected to
1216 * be accessible by the user-space clients, but only accessible by the
1217 * hardware producers and consumers.
1218 *
1219 * The user-space clients should expect a failure while trying to mmap
1220 * the DMA-BUF handle returned by the producer.
1221 */
1222 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1223
1224 /* Amlogic FBC Layout Options Bit Mask */
1225
1226 /*
1227 * Amlogic FBC Memory Saving mode
1228 *
1229 * Indicates the storage is packed when pixel size is multiple of word
1230 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1231 * memory.
1232 *
1233 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1234 * the basic layout and 3200 bytes per 64x32 superblock combined with
1235 * the scatter layout.
1236 */
1237 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1238
1239 /*
1240 * AMD modifiers
1241 *
1242 * Memory layout:
1243 *
1244 * without DCC:
1245 * - main surface
1246 *
1247 * with DCC & without DCC_RETILE:
1248 * - main surface in plane 0
1249 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1250 *
1251 * with DCC & DCC_RETILE:
1252 * - main surface in plane 0
1253 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1254 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1255 *
1256 * For multi-plane formats the above surfaces get merged into one plane for
1257 * each format plane, based on the required alignment only.
1258 *
1259 * Bits Parameter Notes
1260 * ----- ------------------------ ---------------------------------------------
1261 *
1262 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
1263 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1264 * 13 DCC
1265 * 14 DCC_RETILE
1266 * 15 DCC_PIPE_ALIGN
1267 * 16 DCC_INDEPENDENT_64B
1268 * 17 DCC_INDEPENDENT_128B
1269 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1270 * 20 DCC_CONSTANT_ENCODE
1271 * 23:21 PIPE_XOR_BITS Only for some chips
1272 * 26:24 BANK_XOR_BITS Only for some chips
1273 * 29:27 PACKERS Only for some chips
1274 * 32:30 RB Only for some chips
1275 * 35:33 PIPE Only for some chips
1276 * 55:36 - Reserved for future use, must be zero
1277 */
1278 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1279
1280 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1281
1282 /* Reserve 0 for GFX8 and older */
1283 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1284 #define AMD_FMT_MOD_TILE_VER_GFX10 2
1285 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1286
1287 /*
1288 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1289 * version.
1290 */
1291 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1292
1293 /*
1294 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1295 * GFX9 as canonical version.
1296 */
1297 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1298 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1299 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1300 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1301
1302 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
1303 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1304 #define AMD_FMT_MOD_DCC_BLOCK_256B 2
1305
1306 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1307 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1308 #define AMD_FMT_MOD_TILE_SHIFT 8
1309 #define AMD_FMT_MOD_TILE_MASK 0x1F
1310
1311 /* Whether DCC compression is enabled. */
1312 #define AMD_FMT_MOD_DCC_SHIFT 13
1313 #define AMD_FMT_MOD_DCC_MASK 0x1
1314
1315 /*
1316 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1317 * one which is not-aligned.
1318 */
1319 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1320 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1321
1322 /* Only set if DCC_RETILE = false */
1323 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1324 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1325
1326 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1327 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1328 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1329 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1330 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1331 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1332
1333 /*
1334 * DCC supports embedding some clear colors directly in the DCC surface.
1335 * However, on older GPUs the rendering HW ignores the embedded clear color
1336 * and prefers the driver provided color. This necessitates doing a fastclear
1337 * eliminate operation before a process transfers control.
1338 *
1339 * If this bit is set that means the fastclear eliminate is not needed for these
1340 * embeddable colors.
1341 */
1342 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1343 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1344
1345 /*
1346 * The below fields are for accounting for per GPU differences. These are only
1347 * relevant for GFX9 and later and if the tile field is *_X/_T.
1348 *
1349 * PIPE_XOR_BITS = always needed
1350 * BANK_XOR_BITS = only for TILE_VER_GFX9
1351 * PACKERS = only for TILE_VER_GFX10_RBPLUS
1352 * RB = only for TILE_VER_GFX9 & DCC
1353 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1354 */
1355 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1356 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1357 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1358 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1359 #define AMD_FMT_MOD_PACKERS_SHIFT 27
1360 #define AMD_FMT_MOD_PACKERS_MASK 0x7
1361 #define AMD_FMT_MOD_RB_SHIFT 30
1362 #define AMD_FMT_MOD_RB_MASK 0x7
1363 #define AMD_FMT_MOD_PIPE_SHIFT 33
1364 #define AMD_FMT_MOD_PIPE_MASK 0x7
1365
1366 #define AMD_FMT_MOD_SET(field, value) \
1367 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
1368 #define AMD_FMT_MOD_GET(field, value) \
1369 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1370 #define AMD_FMT_MOD_CLEAR(field) \
1371 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1372
1373 #if defined(__cplusplus)
1374 }
1375 #endif
1376
1377 #endif /* DRM_FOURCC_H */
1378