1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key hash lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 62 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 63 #else 64 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 65 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 66 67 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 68 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 69 70 /* The remaining Trusted SRAM is used to load the BL images */ 71 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 72 ARM_SHARED_RAM_SIZE) 73 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 74 ARM_SHARED_RAM_SIZE) 75 76 /* 77 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 78 * follows: 79 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 80 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 81 * - REALM DRAM: Reserved for Realm world if RME is enabled 82 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 83 * 84 * RME enabled(64MB) RME not enabled(16MB) 85 * -------------------- ------------------- 86 * | | | | 87 * | AP TZC (~28MB) | | AP TZC (~14MB) | 88 * -------------------- ------------------- 89 * | | | | 90 * | REALM (32MB) | | EL3 TZC (2MB) | 91 * -------------------- ------------------- 92 * | | | | 93 * | EL3 TZC (3MB) | | SCP TZC | 94 * -------------------- 0xFFFF_FFFF------------------- 95 * | L1 GPT + SCP TZC | 96 * | (~1MB) | 97 * 0xFFFF_FFFF -------------------- 98 */ 99 #if ENABLE_RME 100 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 101 /* 102 * Define a region within the TZC secured DRAM for use by EL3 runtime 103 * firmware. This region is meant to be NOLOAD and will not be zero 104 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 105 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 106 */ 107 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 108 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 109 #define ARM_REALM_SIZE UL(0x02000000) /* 32MB */ 110 #else 111 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 112 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 113 #define ARM_L1_GPT_SIZE UL(0) 114 #define ARM_REALM_SIZE UL(0) 115 #endif /* ENABLE_RME */ 116 117 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 118 ARM_DRAM1_SIZE - \ 119 (ARM_SCP_TZC_DRAM1_SIZE + \ 120 ARM_L1_GPT_SIZE)) 121 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 122 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 123 ARM_SCP_TZC_DRAM1_SIZE - 1U) 124 #if ENABLE_RME 125 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 126 ARM_DRAM1_SIZE - \ 127 ARM_L1_GPT_SIZE) 128 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 129 ARM_L1_GPT_SIZE - 1U) 130 131 #define ARM_REALM_BASE (ARM_DRAM1_BASE + \ 132 ARM_DRAM1_SIZE - \ 133 (ARM_SCP_TZC_DRAM1_SIZE + \ 134 ARM_EL3_TZC_DRAM1_SIZE + \ 135 ARM_REALM_SIZE + \ 136 ARM_L1_GPT_SIZE)) 137 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 138 #endif /* ENABLE_RME */ 139 140 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 141 ARM_EL3_TZC_DRAM1_SIZE) 142 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 143 ARM_EL3_TZC_DRAM1_SIZE - 1U) 144 145 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 146 ARM_DRAM1_SIZE - \ 147 ARM_TZC_DRAM1_SIZE) 148 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 149 (ARM_SCP_TZC_DRAM1_SIZE + \ 150 ARM_EL3_TZC_DRAM1_SIZE + \ 151 ARM_REALM_SIZE + \ 152 ARM_L1_GPT_SIZE)) 153 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 154 ARM_AP_TZC_DRAM1_SIZE - 1U) 155 156 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 157 #if ARM_CRYPTOCELL_INTEG 158 /* 159 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 160 * This is required by CryptoCell to authenticate BL33 which is loaded 161 * into the Non Secure DDR. 162 */ 163 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 164 #else 165 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 166 #endif 167 168 #ifdef SPD_opteed 169 /* 170 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 171 * load/authenticate the trusted os extra image. The first 512KB of 172 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 173 * for OPTEE is paged image which only include the paging part using 174 * virtual memory but without "init" data. OPTEE will copy the "init" data 175 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 176 * extra image behind the "init" data. 177 */ 178 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 179 ARM_AP_TZC_DRAM1_SIZE - \ 180 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 181 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 182 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 183 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 184 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 185 MT_MEMORY | MT_RW | MT_SECURE) 186 187 /* 188 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 189 * support is enabled). 190 */ 191 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 192 BL32_BASE, \ 193 BL32_LIMIT - BL32_BASE, \ 194 MT_MEMORY | MT_RW | MT_SECURE) 195 #endif /* SPD_opteed */ 196 197 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 198 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 199 ARM_TZC_DRAM1_SIZE) 200 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 201 ARM_NS_DRAM1_SIZE - 1U) 202 #ifdef PLAT_ARM_DRAM1_BASE 203 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 204 #else 205 #define ARM_DRAM1_BASE ULL(0x80000000) 206 #endif /* PLAT_ARM_DRAM1_BASE */ 207 208 #define ARM_DRAM1_SIZE ULL(0x80000000) 209 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 210 ARM_DRAM1_SIZE - 1U) 211 212 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 213 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 214 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 215 ARM_DRAM2_SIZE - 1U) 216 217 #define ARM_IRQ_SEC_PHY_TIMER 29 218 219 #define ARM_IRQ_SEC_SGI_0 8 220 #define ARM_IRQ_SEC_SGI_1 9 221 #define ARM_IRQ_SEC_SGI_2 10 222 #define ARM_IRQ_SEC_SGI_3 11 223 #define ARM_IRQ_SEC_SGI_4 12 224 #define ARM_IRQ_SEC_SGI_5 13 225 #define ARM_IRQ_SEC_SGI_6 14 226 #define ARM_IRQ_SEC_SGI_7 15 227 228 /* 229 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 230 * terminology. On a GICv2 system or mode, the lists will be merged and treated 231 * as Group 0 interrupts. 232 */ 233 #define ARM_G1S_IRQ_PROPS(grp) \ 234 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 235 GIC_INTR_CFG_LEVEL), \ 236 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 237 GIC_INTR_CFG_EDGE), \ 238 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 239 GIC_INTR_CFG_EDGE), \ 240 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 241 GIC_INTR_CFG_EDGE), \ 242 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 243 GIC_INTR_CFG_EDGE), \ 244 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 245 GIC_INTR_CFG_EDGE), \ 246 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 247 GIC_INTR_CFG_EDGE) 248 249 #define ARM_G0_IRQ_PROPS(grp) \ 250 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 251 GIC_INTR_CFG_EDGE), \ 252 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 253 GIC_INTR_CFG_EDGE) 254 255 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 256 ARM_SHARED_RAM_BASE, \ 257 ARM_SHARED_RAM_SIZE, \ 258 MT_DEVICE | MT_RW | EL3_PAS) 259 260 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 261 ARM_NS_DRAM1_BASE, \ 262 ARM_NS_DRAM1_SIZE, \ 263 MT_MEMORY | MT_RW | MT_NS) 264 265 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 266 ARM_DRAM2_BASE, \ 267 ARM_DRAM2_SIZE, \ 268 MT_MEMORY | MT_RW | MT_NS) 269 270 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 271 TSP_SEC_MEM_BASE, \ 272 TSP_SEC_MEM_SIZE, \ 273 MT_MEMORY | MT_RW | MT_SECURE) 274 275 #if ARM_BL31_IN_DRAM 276 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 277 BL31_BASE, \ 278 PLAT_ARM_MAX_BL31_SIZE, \ 279 MT_MEMORY | MT_RW | MT_SECURE) 280 #endif 281 282 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 283 ARM_EL3_TZC_DRAM1_BASE, \ 284 ARM_EL3_TZC_DRAM1_SIZE, \ 285 MT_MEMORY | MT_RW | EL3_PAS) 286 287 #if defined(SPD_spmd) 288 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 289 PLAT_ARM_TRUSTED_DRAM_BASE, \ 290 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 291 MT_MEMORY | MT_RW | MT_SECURE) 292 #endif 293 294 #if ENABLE_RME 295 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 296 PLAT_ARM_RMM_BASE, \ 297 PLAT_ARM_RMM_SIZE, \ 298 MT_MEMORY | MT_RW | MT_REALM) 299 300 301 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 302 ARM_L1_GPT_ADDR_BASE, \ 303 ARM_L1_GPT_SIZE, \ 304 MT_MEMORY | MT_RW | EL3_PAS) 305 306 #endif /* ENABLE_RME */ 307 308 /* 309 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 310 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 311 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 312 * to be able to access the heap. 313 */ 314 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 315 BL1_RW_BASE, \ 316 BL1_RW_LIMIT - BL1_RW_BASE, \ 317 MT_MEMORY | MT_RW | EL3_PAS) 318 319 /* 320 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 321 * otherwise one region is defined containing both. 322 */ 323 #if SEPARATE_CODE_AND_RODATA 324 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 325 BL_CODE_BASE, \ 326 BL_CODE_END - BL_CODE_BASE, \ 327 MT_CODE | EL3_PAS), \ 328 MAP_REGION_FLAT( \ 329 BL_RO_DATA_BASE, \ 330 BL_RO_DATA_END \ 331 - BL_RO_DATA_BASE, \ 332 MT_RO_DATA | EL3_PAS) 333 #else 334 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 335 BL_CODE_BASE, \ 336 BL_CODE_END - BL_CODE_BASE, \ 337 MT_CODE | EL3_PAS) 338 #endif 339 #if USE_COHERENT_MEM 340 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 341 BL_COHERENT_RAM_BASE, \ 342 BL_COHERENT_RAM_END \ 343 - BL_COHERENT_RAM_BASE, \ 344 MT_DEVICE | MT_RW | EL3_PAS) 345 #endif 346 #if USE_ROMLIB 347 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 348 ROMLIB_RO_BASE, \ 349 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 350 MT_CODE | EL3_PAS) 351 352 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 353 ROMLIB_RW_BASE, \ 354 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 355 MT_MEMORY | MT_RW | EL3_PAS) 356 #endif 357 358 /* 359 * Map mem_protect flash region with read and write permissions 360 */ 361 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 362 V2M_FLASH_BLOCK_SIZE, \ 363 MT_DEVICE | MT_RW | MT_SECURE) 364 /* 365 * Map the region for device tree configuration with read and write permissions 366 */ 367 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 368 (ARM_FW_CONFIGS_LIMIT \ 369 - ARM_BL_RAM_BASE), \ 370 MT_MEMORY | MT_RW | EL3_PAS) 371 /* 372 * Map L0_GPT with read and write permissions 373 */ 374 #if ENABLE_RME 375 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 376 ARM_L0_GPT_SIZE, \ 377 MT_MEMORY | MT_RW | MT_ROOT) 378 #endif 379 380 /* 381 * The max number of regions like RO(code), coherent and data required by 382 * different BL stages which need to be mapped in the MMU. 383 */ 384 #define ARM_BL_REGIONS 6 385 386 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 387 ARM_BL_REGIONS) 388 389 /* Memory mapped Generic timer interfaces */ 390 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 391 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 392 #else 393 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 394 #endif 395 396 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 397 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 398 #else 399 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 400 #endif 401 402 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 403 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 404 #else 405 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 406 #endif 407 408 #ifdef PLAT_ARM_SYS_CNT_BASE_S 409 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 410 #else 411 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 412 #endif 413 414 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 415 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 416 #else 417 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 418 #endif 419 420 #define ARM_CONSOLE_BAUDRATE 115200 421 422 /* Trusted Watchdog constants */ 423 #ifdef PLAT_ARM_SP805_TWDG_BASE 424 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 425 #else 426 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 427 #endif 428 #define ARM_SP805_TWDG_CLK_HZ 32768 429 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 430 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 431 #define ARM_TWDG_TIMEOUT_SEC 128 432 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 433 ARM_TWDG_TIMEOUT_SEC) 434 435 /****************************************************************************** 436 * Required platform porting definitions common to all ARM standard platforms 437 *****************************************************************************/ 438 439 /* 440 * This macro defines the deepest retention state possible. A higher state 441 * id will represent an invalid or a power down state. 442 */ 443 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 444 445 /* 446 * This macro defines the deepest power down states possible. Any state ID 447 * higher than this is invalid. 448 */ 449 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 450 451 /* 452 * Some data must be aligned on the biggest cache line size in the platform. 453 * This is known only to the platform as it might have a combination of 454 * integrated and external caches. 455 */ 456 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 457 458 /* 459 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 460 * and limit. Leave enough space of BL2 meminfo. 461 */ 462 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 463 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 464 + (PAGE_SIZE / 2U)) 465 466 /* 467 * Boot parameters passed from BL2 to BL31/BL32 are stored here 468 */ 469 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 470 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 471 + (PAGE_SIZE / 2U)) 472 473 /* 474 * Define limit of firmware configuration memory: 475 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 476 */ 477 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 478 479 #if ENABLE_RME 480 /* 481 * Store the L0 GPT on Trusted SRAM next to firmware 482 * configuration memory, 4KB aligned. 483 */ 484 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 485 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 486 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 487 #else 488 #define ARM_L0_GPT_SIZE U(0) 489 #endif 490 491 /******************************************************************************* 492 * BL1 specific defines. 493 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 494 * addresses. 495 ******************************************************************************/ 496 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 497 #ifdef PLAT_BL1_RO_LIMIT 498 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 499 #else 500 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 501 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 502 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 503 #endif 504 505 /* 506 * Put BL1 RW at the top of the Trusted SRAM. 507 */ 508 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 509 ARM_BL_RAM_SIZE - \ 510 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 511 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 512 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 513 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 514 515 #define ROMLIB_RO_BASE BL1_RO_LIMIT 516 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 517 518 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 519 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 520 521 /******************************************************************************* 522 * BL2 specific defines. 523 ******************************************************************************/ 524 #if BL2_AT_EL3 525 /* Put BL2 towards the middle of the Trusted SRAM */ 526 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 527 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 528 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 529 530 #else 531 /* 532 * Put BL2 just below BL1. 533 */ 534 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 535 #define BL2_LIMIT BL1_RW_BASE 536 #endif 537 538 /******************************************************************************* 539 * BL31 specific defines. 540 ******************************************************************************/ 541 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 542 /* 543 * Put BL31 at the bottom of TZC secured DRAM 544 */ 545 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 546 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 547 PLAT_ARM_MAX_BL31_SIZE) 548 /* 549 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 550 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 551 */ 552 #if SEPARATE_NOBITS_REGION 553 #define BL31_NOBITS_BASE BL2_BASE 554 #define BL31_NOBITS_LIMIT BL2_LIMIT 555 #endif /* SEPARATE_NOBITS_REGION */ 556 #elif (RESET_TO_BL31) 557 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 558 # if !ENABLE_PIE 559 # error "BL31 must be a PIE if RESET_TO_BL31=1." 560 #endif 561 /* 562 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 563 * used for building BL31 and not used for loading BL31. 564 */ 565 # define BL31_BASE 0x0 566 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 567 #else 568 /* Put BL31 below BL2 in the Trusted SRAM.*/ 569 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 570 - PLAT_ARM_MAX_BL31_SIZE) 571 #define BL31_PROGBITS_LIMIT BL2_BASE 572 /* 573 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 574 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 575 */ 576 #if BL2_AT_EL3 577 #define BL31_LIMIT BL2_BASE 578 #else 579 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 580 #endif 581 #endif 582 583 /****************************************************************************** 584 * RMM specific defines 585 *****************************************************************************/ 586 #if ENABLE_RME 587 #define RMM_BASE (ARM_REALM_BASE) 588 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 589 #endif 590 591 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 592 /******************************************************************************* 593 * BL32 specific defines for EL3 runtime in AArch32 mode 594 ******************************************************************************/ 595 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 596 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 597 # if !ENABLE_PIE 598 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 599 #endif 600 /* 601 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 602 * used for building BL32 and not used for loading BL32. 603 */ 604 # define BL32_BASE 0x0 605 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 606 # else 607 /* Put BL32 below BL2 in the Trusted SRAM.*/ 608 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 609 - PLAT_ARM_MAX_BL32_SIZE) 610 # define BL32_PROGBITS_LIMIT BL2_BASE 611 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 612 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 613 614 #else 615 /******************************************************************************* 616 * BL32 specific defines for EL3 runtime in AArch64 mode 617 ******************************************************************************/ 618 /* 619 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 620 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 621 * controller. 622 */ 623 # if SPM_MM 624 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 625 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 626 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 627 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 628 ARM_AP_TZC_DRAM1_SIZE) 629 # elif defined(SPD_spmd) 630 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 631 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 632 # define BL32_BASE PLAT_ARM_SPMC_BASE 633 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 634 PLAT_ARM_SPMC_SIZE) 635 # elif ARM_BL31_IN_DRAM 636 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 637 PLAT_ARM_MAX_BL31_SIZE) 638 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 639 PLAT_ARM_MAX_BL31_SIZE) 640 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 641 PLAT_ARM_MAX_BL31_SIZE) 642 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 643 ARM_AP_TZC_DRAM1_SIZE) 644 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 645 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 646 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 647 # define TSP_PROGBITS_LIMIT BL31_BASE 648 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 649 # define BL32_LIMIT BL31_BASE 650 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 651 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 652 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 653 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 654 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 655 + (UL(1) << 21)) 656 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 657 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 658 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 659 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 660 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 661 ARM_AP_TZC_DRAM1_SIZE) 662 # else 663 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 664 # endif 665 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 666 667 /* 668 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 669 * SPD and no SPM-MM, as they are the only ones that can be used as BL32. 670 */ 671 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 672 # if defined(SPD_none) && !SPM_MM 673 # undef BL32_BASE 674 # endif /* defined(SPD_none) && !SPM_MM */ 675 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 676 677 /******************************************************************************* 678 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 679 ******************************************************************************/ 680 #define BL2U_BASE BL2_BASE 681 #define BL2U_LIMIT BL2_LIMIT 682 683 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 684 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 685 686 /* 687 * ID of the secure physical generic timer interrupt used by the TSP. 688 */ 689 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 690 691 692 /* 693 * One cache line needed for bakery locks on ARM platforms 694 */ 695 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 696 697 /* Priority levels for ARM platforms */ 698 #define PLAT_RAS_PRI 0x10 699 #define PLAT_SDEI_CRITICAL_PRI 0x60 700 #define PLAT_SDEI_NORMAL_PRI 0x70 701 702 /* ARM platforms use 3 upper bits of secure interrupt priority */ 703 #define PLAT_PRI_BITS 3 704 705 /* SGI used for SDEI signalling */ 706 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 707 708 #if SDEI_IN_FCONF 709 /* ARM SDEI dynamic private event max count */ 710 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 711 712 /* ARM SDEI dynamic shared event max count */ 713 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 714 #else 715 /* ARM SDEI dynamic private event numbers */ 716 #define ARM_SDEI_DP_EVENT_0 1000 717 #define ARM_SDEI_DP_EVENT_1 1001 718 #define ARM_SDEI_DP_EVENT_2 1002 719 720 /* ARM SDEI dynamic shared event numbers */ 721 #define ARM_SDEI_DS_EVENT_0 2000 722 #define ARM_SDEI_DS_EVENT_1 2001 723 #define ARM_SDEI_DS_EVENT_2 2002 724 725 #define ARM_SDEI_PRIVATE_EVENTS \ 726 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 727 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 728 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 729 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 730 731 #define ARM_SDEI_SHARED_EVENTS \ 732 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 733 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 734 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 735 #endif /* SDEI_IN_FCONF */ 736 737 #endif /* ARM_DEF_H */ 738