1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_PAS_DEF_H 7 #define ARM_PAS_DEF_H 8 9 #include <lib/gpt_rme/gpt_rme.h> 10 #include <plat/arm/common/arm_def.h> 11 12 /***************************************************************************** 13 * PAS regions used to initialize the Granule Protection Table (GPT) 14 ****************************************************************************/ 15 16 /* 17 * The PA space is initially mapped in the GPT as follows: 18 * 19 * ============================================================================ 20 * Base Addr| Size |L? GPT|PAS |Content |Comment 21 * ============================================================================ 22 * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping 23 * | | | |TSRAM (EL3 data) | 24 * | | | |IO (incl.UARTs & GIC) | 25 * ---------------------------------------------------------------------------- 26 * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping 27 * ---------------------------------------------------------------------------- 28 * 2GB | 1GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 29 * ---------------------------------------------------------------------------- 30 * 3GB |1GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 31 * ---------------------------------------------------------------------------- 32 * 4GB-64MB |64MB-32MB | | | | 33 * | -4MB |L1 GPT|SECURE|DRAM TZC |Use T.Descrip 34 * ---------------------------------------------------------------------------- 35 * 4GB-32MB | | | | | 36 * -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip 37 * ---------------------------------------------------------------------------- 38 * 4GB-3MB | | | | | 39 * -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip 40 * ---------------------------------------------------------------------------- 41 * 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping 42 * ============================================================================ 43 * 44 * - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section. 45 * - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area). 46 * - The first 1GB region has GPT_GPI_ANY and, therefore, is not protected by 47 * the GPT. 48 * - The DRAM TZC area is split into three regions: the L1 GPT region and 49 * 3MB of region below that are defined as GPT_GPI_ROOT, 32MB Realm region 50 * below that is defined as GPT_GPI_REALM and the rest of it is defined as 51 * GPT_GPI_SECURE. 52 */ 53 54 /* TODO: This might not be the best way to map the PAS */ 55 56 /* Device memory 0 to 2GB */ 57 #define ARM_PAS_1_BASE (U(0)) 58 #define ARM_PAS_1_SIZE ((ULL(1)<<31)) /* 2GB */ 59 60 /* NS memory 2GB to (end - 64MB) */ 61 #define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) 62 #define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) 63 64 /* Secure TZC region */ 65 #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) 66 #define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) 67 68 #define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \ 69 ARM_PAS_1_SIZE, \ 70 GPT_GPI_ANY) 71 #define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \ 72 ARM_PAS_2_SIZE, \ 73 GPT_GPI_NS) 74 75 #define ARM_PAS_SECURE GPT_MAP_REGION_GRANULE(ARM_PAS_3_BASE, \ 76 ARM_PAS_3_SIZE, \ 77 GPT_GPI_SECURE) 78 79 #define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \ 80 ARM_REALM_SIZE, \ 81 GPT_GPI_REALM) 82 83 #define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ 84 ARM_EL3_TZC_DRAM1_SIZE, \ 85 GPT_GPI_ROOT) 86 87 #define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_ADDR_BASE, \ 88 ARM_L1_GPT_SIZE, \ 89 GPT_GPI_ROOT) 90 91 /* GPT Configuration options */ 92 #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS 93 94 #endif /* ARM_PAS_DEF_H */ 95