1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key hash lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 /* The first 4KB of Trusted SRAM are used as shared memory */ 62 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 63 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 64 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 65 66 /* The remaining Trusted SRAM is used to load the BL images */ 67 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 68 ARM_SHARED_RAM_SIZE) 69 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 70 ARM_SHARED_RAM_SIZE) 71 72 /* 73 * The top 16MB of DRAM1 is configured as secure access only using the TZC 74 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 75 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 76 */ 77 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 78 79 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 80 ARM_DRAM1_SIZE - \ 81 ARM_SCP_TZC_DRAM1_SIZE) 82 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 83 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 84 ARM_SCP_TZC_DRAM1_SIZE - 1U) 85 86 /* 87 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 88 * firmware. This region is meant to be NOLOAD and will not be zero 89 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 90 * placed here. 91 */ 92 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 93 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 94 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 95 ARM_EL3_TZC_DRAM1_SIZE - 1U) 96 97 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 98 ARM_DRAM1_SIZE - \ 99 ARM_TZC_DRAM1_SIZE) 100 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 101 (ARM_SCP_TZC_DRAM1_SIZE + \ 102 ARM_EL3_TZC_DRAM1_SIZE)) 103 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 104 ARM_AP_TZC_DRAM1_SIZE - 1U) 105 106 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 107 #if ARM_CRYPTOCELL_INTEG 108 /* 109 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 110 * This is required by CryptoCell to authenticate BL33 which is loaded 111 * into the Non Secure DDR. 112 */ 113 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 114 #else 115 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 116 #endif 117 118 #ifdef SPD_opteed 119 /* 120 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 121 * load/authenticate the trusted os extra image. The first 512KB of 122 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 123 * for OPTEE is paged image which only include the paging part using 124 * virtual memory but without "init" data. OPTEE will copy the "init" data 125 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 126 * extra image behind the "init" data. 127 */ 128 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 129 ARM_AP_TZC_DRAM1_SIZE - \ 130 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 131 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 132 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 133 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 134 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 135 MT_MEMORY | MT_RW | MT_SECURE) 136 137 /* 138 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 139 * support is enabled). 140 */ 141 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 142 BL32_BASE, \ 143 BL32_LIMIT - BL32_BASE, \ 144 MT_MEMORY | MT_RW | MT_SECURE) 145 #endif /* SPD_opteed */ 146 147 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 148 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 149 ARM_TZC_DRAM1_SIZE) 150 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 151 ARM_NS_DRAM1_SIZE - 1U) 152 153 #define ARM_DRAM1_BASE ULL(0x80000000) 154 #define ARM_DRAM1_SIZE ULL(0x80000000) 155 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 156 ARM_DRAM1_SIZE - 1U) 157 158 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 159 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 160 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 161 ARM_DRAM2_SIZE - 1U) 162 163 #define ARM_IRQ_SEC_PHY_TIMER 29 164 165 #define ARM_IRQ_SEC_SGI_0 8 166 #define ARM_IRQ_SEC_SGI_1 9 167 #define ARM_IRQ_SEC_SGI_2 10 168 #define ARM_IRQ_SEC_SGI_3 11 169 #define ARM_IRQ_SEC_SGI_4 12 170 #define ARM_IRQ_SEC_SGI_5 13 171 #define ARM_IRQ_SEC_SGI_6 14 172 #define ARM_IRQ_SEC_SGI_7 15 173 174 /* 175 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 176 * terminology. On a GICv2 system or mode, the lists will be merged and treated 177 * as Group 0 interrupts. 178 */ 179 #define ARM_G1S_IRQ_PROPS(grp) \ 180 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 181 GIC_INTR_CFG_LEVEL), \ 182 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 183 GIC_INTR_CFG_EDGE), \ 184 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 185 GIC_INTR_CFG_EDGE), \ 186 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 187 GIC_INTR_CFG_EDGE), \ 188 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 189 GIC_INTR_CFG_EDGE), \ 190 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 191 GIC_INTR_CFG_EDGE), \ 192 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 193 GIC_INTR_CFG_EDGE) 194 195 #define ARM_G0_IRQ_PROPS(grp) \ 196 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 197 GIC_INTR_CFG_EDGE), \ 198 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 199 GIC_INTR_CFG_EDGE) 200 201 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 202 ARM_SHARED_RAM_BASE, \ 203 ARM_SHARED_RAM_SIZE, \ 204 MT_DEVICE | MT_RW | MT_SECURE) 205 206 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 207 ARM_NS_DRAM1_BASE, \ 208 ARM_NS_DRAM1_SIZE, \ 209 MT_MEMORY | MT_RW | MT_NS) 210 211 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 212 ARM_DRAM2_BASE, \ 213 ARM_DRAM2_SIZE, \ 214 MT_MEMORY | MT_RW | MT_NS) 215 216 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 217 TSP_SEC_MEM_BASE, \ 218 TSP_SEC_MEM_SIZE, \ 219 MT_MEMORY | MT_RW | MT_SECURE) 220 221 #if ARM_BL31_IN_DRAM 222 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 223 BL31_BASE, \ 224 PLAT_ARM_MAX_BL31_SIZE, \ 225 MT_MEMORY | MT_RW | MT_SECURE) 226 #endif 227 228 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 229 ARM_EL3_TZC_DRAM1_BASE, \ 230 ARM_EL3_TZC_DRAM1_SIZE, \ 231 MT_MEMORY | MT_RW | MT_SECURE) 232 233 #if defined(SPD_spmd) 234 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 235 PLAT_ARM_TRUSTED_DRAM_BASE, \ 236 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 237 MT_MEMORY | MT_RW | MT_SECURE) 238 #endif 239 240 241 /* 242 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 243 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 244 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 245 * to be able to access the heap. 246 */ 247 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 248 BL1_RW_BASE, \ 249 BL1_RW_LIMIT - BL1_RW_BASE, \ 250 MT_MEMORY | MT_RW | MT_SECURE) 251 252 /* 253 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 254 * otherwise one region is defined containing both. 255 */ 256 #if SEPARATE_CODE_AND_RODATA 257 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 258 BL_CODE_BASE, \ 259 BL_CODE_END - BL_CODE_BASE, \ 260 MT_CODE | MT_SECURE), \ 261 MAP_REGION_FLAT( \ 262 BL_RO_DATA_BASE, \ 263 BL_RO_DATA_END \ 264 - BL_RO_DATA_BASE, \ 265 MT_RO_DATA | MT_SECURE) 266 #else 267 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 268 BL_CODE_BASE, \ 269 BL_CODE_END - BL_CODE_BASE, \ 270 MT_CODE | MT_SECURE) 271 #endif 272 #if USE_COHERENT_MEM 273 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 274 BL_COHERENT_RAM_BASE, \ 275 BL_COHERENT_RAM_END \ 276 - BL_COHERENT_RAM_BASE, \ 277 MT_DEVICE | MT_RW | MT_SECURE) 278 #endif 279 #if USE_ROMLIB 280 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 281 ROMLIB_RO_BASE, \ 282 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 283 MT_CODE | MT_SECURE) 284 285 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 286 ROMLIB_RW_BASE, \ 287 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 288 MT_MEMORY | MT_RW | MT_SECURE) 289 #endif 290 291 /* 292 * Map mem_protect flash region with read and write permissions 293 */ 294 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 295 V2M_FLASH_BLOCK_SIZE, \ 296 MT_DEVICE | MT_RW | MT_SECURE) 297 /* 298 * Map the region for device tree configuration with read and write permissions 299 */ 300 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 301 (ARM_FW_CONFIGS_LIMIT \ 302 - ARM_BL_RAM_BASE), \ 303 MT_MEMORY | MT_RW | MT_SECURE) 304 305 /* 306 * The max number of regions like RO(code), coherent and data required by 307 * different BL stages which need to be mapped in the MMU. 308 */ 309 #define ARM_BL_REGIONS 6 310 311 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 312 ARM_BL_REGIONS) 313 314 /* Memory mapped Generic timer interfaces */ 315 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 316 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 317 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 318 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 319 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 320 321 #define ARM_CONSOLE_BAUDRATE 115200 322 323 /* Trusted Watchdog constants */ 324 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 325 #define ARM_SP805_TWDG_CLK_HZ 32768 326 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 327 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 328 #define ARM_TWDG_TIMEOUT_SEC 128 329 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 330 ARM_TWDG_TIMEOUT_SEC) 331 332 /****************************************************************************** 333 * Required platform porting definitions common to all ARM standard platforms 334 *****************************************************************************/ 335 336 /* 337 * This macro defines the deepest retention state possible. A higher state 338 * id will represent an invalid or a power down state. 339 */ 340 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 341 342 /* 343 * This macro defines the deepest power down states possible. Any state ID 344 * higher than this is invalid. 345 */ 346 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 347 348 /* 349 * Some data must be aligned on the biggest cache line size in the platform. 350 * This is known only to the platform as it might have a combination of 351 * integrated and external caches. 352 */ 353 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 354 355 /* 356 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 357 * and limit. Leave enough space of BL2 meminfo. 358 */ 359 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 360 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 361 + (PAGE_SIZE / 2U)) 362 363 /* 364 * Boot parameters passed from BL2 to BL31/BL32 are stored here 365 */ 366 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 367 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 368 + (PAGE_SIZE / 2U)) 369 370 /* 371 * Define limit of firmware configuration memory: 372 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 373 */ 374 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 375 376 /******************************************************************************* 377 * BL1 specific defines. 378 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 379 * addresses. 380 ******************************************************************************/ 381 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 382 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 383 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 384 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 385 /* 386 * Put BL1 RW at the top of the Trusted SRAM. 387 */ 388 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 389 ARM_BL_RAM_SIZE - \ 390 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 391 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 392 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 393 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 394 395 #define ROMLIB_RO_BASE BL1_RO_LIMIT 396 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 397 398 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 399 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 400 401 /******************************************************************************* 402 * BL2 specific defines. 403 ******************************************************************************/ 404 #if BL2_AT_EL3 405 /* Put BL2 towards the middle of the Trusted SRAM */ 406 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 407 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 408 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 409 410 #else 411 /* 412 * Put BL2 just below BL1. 413 */ 414 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 415 #define BL2_LIMIT BL1_RW_BASE 416 #endif 417 418 /******************************************************************************* 419 * BL31 specific defines. 420 ******************************************************************************/ 421 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 422 /* 423 * Put BL31 at the bottom of TZC secured DRAM 424 */ 425 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 426 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 427 PLAT_ARM_MAX_BL31_SIZE) 428 /* 429 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 430 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 431 */ 432 #if SEPARATE_NOBITS_REGION 433 #define BL31_NOBITS_BASE BL2_BASE 434 #define BL31_NOBITS_LIMIT BL2_LIMIT 435 #endif /* SEPARATE_NOBITS_REGION */ 436 #elif (RESET_TO_BL31) 437 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 438 # if !ENABLE_PIE 439 # error "BL31 must be a PIE if RESET_TO_BL31=1." 440 #endif 441 /* 442 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 443 * used for building BL31 and not used for loading BL31. 444 */ 445 # define BL31_BASE 0x0 446 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 447 #else 448 /* Put BL31 below BL2 in the Trusted SRAM.*/ 449 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 450 - PLAT_ARM_MAX_BL31_SIZE) 451 #define BL31_PROGBITS_LIMIT BL2_BASE 452 /* 453 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 454 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 455 */ 456 #if BL2_AT_EL3 457 #define BL31_LIMIT BL2_BASE 458 #else 459 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 460 #endif 461 #endif 462 463 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 464 /******************************************************************************* 465 * BL32 specific defines for EL3 runtime in AArch32 mode 466 ******************************************************************************/ 467 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 468 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 469 # if !ENABLE_PIE 470 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 471 #endif 472 /* 473 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 474 * used for building BL32 and not used for loading BL32. 475 */ 476 # define BL32_BASE 0x0 477 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 478 # else 479 /* Put BL32 below BL2 in the Trusted SRAM.*/ 480 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 481 - PLAT_ARM_MAX_BL32_SIZE) 482 # define BL32_PROGBITS_LIMIT BL2_BASE 483 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 484 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 485 486 #else 487 /******************************************************************************* 488 * BL32 specific defines for EL3 runtime in AArch64 mode 489 ******************************************************************************/ 490 /* 491 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 492 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 493 * controller. 494 */ 495 # if SPM_MM || SPMC_AT_EL3 496 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 497 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 498 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 499 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 500 ARM_AP_TZC_DRAM1_SIZE) 501 # elif defined(SPD_spmd) 502 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 503 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 504 # define BL32_BASE PLAT_ARM_SPMC_BASE 505 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 506 PLAT_ARM_SPMC_SIZE) 507 # elif ARM_BL31_IN_DRAM 508 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 509 PLAT_ARM_MAX_BL31_SIZE) 510 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 511 PLAT_ARM_MAX_BL31_SIZE) 512 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 513 PLAT_ARM_MAX_BL31_SIZE) 514 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 515 ARM_AP_TZC_DRAM1_SIZE) 516 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 517 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 518 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 519 # define TSP_PROGBITS_LIMIT BL31_BASE 520 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 521 # define BL32_LIMIT BL31_BASE 522 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 523 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 524 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 525 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 526 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 527 + (UL(1) << 21)) 528 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 529 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 530 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 531 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 532 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 533 ARM_AP_TZC_DRAM1_SIZE) 534 # else 535 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 536 # endif 537 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 538 539 /* 540 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 541 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 542 * used as BL32. 543 */ 544 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 545 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 546 # undef BL32_BASE 547 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3*/ 548 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 549 550 /******************************************************************************* 551 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 552 ******************************************************************************/ 553 #define BL2U_BASE BL2_BASE 554 #define BL2U_LIMIT BL2_LIMIT 555 556 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 557 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 558 559 /* 560 * ID of the secure physical generic timer interrupt used by the TSP. 561 */ 562 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 563 564 565 /* 566 * One cache line needed for bakery locks on ARM platforms 567 */ 568 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 569 570 /* Priority levels for ARM platforms */ 571 #define PLAT_RAS_PRI 0x10 572 #define PLAT_SDEI_CRITICAL_PRI 0x60 573 #define PLAT_SDEI_NORMAL_PRI 0x70 574 575 /* ARM platforms use 3 upper bits of secure interrupt priority */ 576 #define PLAT_PRI_BITS 3 577 578 /* SGI used for SDEI signalling */ 579 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 580 581 #if SDEI_IN_FCONF 582 /* ARM SDEI dynamic private event max count */ 583 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 584 585 /* ARM SDEI dynamic shared event max count */ 586 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 587 #else 588 /* ARM SDEI dynamic private event numbers */ 589 #define ARM_SDEI_DP_EVENT_0 1000 590 #define ARM_SDEI_DP_EVENT_1 1001 591 #define ARM_SDEI_DP_EVENT_2 1002 592 593 /* ARM SDEI dynamic shared event numbers */ 594 #define ARM_SDEI_DS_EVENT_0 2000 595 #define ARM_SDEI_DS_EVENT_1 2001 596 #define ARM_SDEI_DS_EVENT_2 2002 597 598 #define ARM_SDEI_PRIVATE_EVENTS \ 599 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 600 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 601 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 602 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 603 604 #define ARM_SDEI_SHARED_EVENTS \ 605 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 606 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 607 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 608 #endif /* SDEI_IN_FCONF */ 609 610 #endif /* ARM_DEF_H */ 611