1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * The above copyright notice and this permission notice (including the
21  * next paragraph) shall be included in all copies or substantial portions
22  * of the Software.
23  *
24  */
25 /*
26  * Authors: Dave Airlie <airlied@redhat.com>
27  */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30 
31 #include <linux/i2c.h>
32 #include <linux/i2c-algo-bit.h>
33 #include <linux/io.h>
34 #include <linux/types.h>
35 
36 #include <drm/drm_connector.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_mode.h>
40 #include <drm/drm_framebuffer.h>
41 #include <drm/drm_fb_helper.h>
42 
43 #define DRIVER_AUTHOR		"Dave Airlie"
44 
45 #define DRIVER_NAME		"ast"
46 #define DRIVER_DESC		"AST"
47 #define DRIVER_DATE		"20120228"
48 
49 #define DRIVER_MAJOR		0
50 #define DRIVER_MINOR		1
51 #define DRIVER_PATCHLEVEL	0
52 
53 #define PCI_CHIP_AST2000 0x2000
54 #define PCI_CHIP_AST2100 0x2010
55 
56 
57 enum ast_chip {
58 	AST2000,
59 	AST2100,
60 	AST1100,
61 	AST2200,
62 	AST2150,
63 	AST2300,
64 	AST2400,
65 	AST2500,
66 	AST2600,
67 };
68 
69 enum ast_tx_chip {
70 	AST_TX_NONE,
71 	AST_TX_SIL164,
72 	AST_TX_ITE66121,
73 	AST_TX_DP501,
74 };
75 
76 #define AST_DRAM_512Mx16 0
77 #define AST_DRAM_1Gx16   1
78 #define AST_DRAM_512Mx32 2
79 #define AST_DRAM_1Gx32   3
80 #define AST_DRAM_2Gx16   6
81 #define AST_DRAM_4Gx16   7
82 #define AST_DRAM_8Gx16   8
83 
84 /*
85  * Cursor plane
86  */
87 
88 #define AST_MAX_HWC_WIDTH	64
89 #define AST_MAX_HWC_HEIGHT	64
90 
91 #define AST_HWC_SIZE		(AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
92 #define AST_HWC_SIGNATURE_SIZE	32
93 
94 #define AST_DEFAULT_HWC_NUM	2
95 
96 /* define for signature structure */
97 #define AST_HWC_SIGNATURE_CHECKSUM	0x00
98 #define AST_HWC_SIGNATURE_SizeX		0x04
99 #define AST_HWC_SIGNATURE_SizeY		0x08
100 #define AST_HWC_SIGNATURE_X		0x0C
101 #define AST_HWC_SIGNATURE_Y		0x10
102 #define AST_HWC_SIGNATURE_HOTSPOTX	0x14
103 #define AST_HWC_SIGNATURE_HOTSPOTY	0x18
104 
105 struct ast_cursor_plane {
106 	struct drm_plane base;
107 
108 	struct {
109 		struct drm_gem_vram_object *gbo;
110 		struct dma_buf_map map;
111 		u64 off;
112 	} hwc[AST_DEFAULT_HWC_NUM];
113 
114 	unsigned int next_hwc_index;
115 };
116 
117 static inline struct ast_cursor_plane *
to_ast_cursor_plane(struct drm_plane * plane)118 to_ast_cursor_plane(struct drm_plane *plane)
119 {
120 	return container_of(plane, struct ast_cursor_plane, base);
121 }
122 
123 /*
124  * Connector with i2c channel
125  */
126 
127 struct ast_i2c_chan {
128 	struct i2c_adapter adapter;
129 	struct drm_device *dev;
130 	struct i2c_algo_bit_data bit;
131 };
132 
133 struct ast_connector {
134 	struct drm_connector base;
135 	struct ast_i2c_chan *i2c;
136 };
137 
138 static inline struct ast_connector *
to_ast_connector(struct drm_connector * connector)139 to_ast_connector(struct drm_connector *connector)
140 {
141 	return container_of(connector, struct ast_connector, base);
142 }
143 
144 /*
145  * Device
146  */
147 
148 struct ast_private {
149 	struct drm_device base;
150 
151 	void __iomem *regs;
152 	void __iomem *ioregs;
153 	void __iomem *dp501_fw_buf;
154 
155 	enum ast_chip chip;
156 	bool vga2_clone;
157 	uint32_t dram_bus_width;
158 	uint32_t dram_type;
159 	uint32_t mclk;
160 
161 	struct drm_plane primary_plane;
162 	struct ast_cursor_plane cursor_plane;
163 	struct drm_crtc crtc;
164 	struct drm_encoder encoder;
165 	struct ast_connector connector;
166 
167 	bool support_wide_screen;
168 	enum {
169 		ast_use_p2a,
170 		ast_use_dt,
171 		ast_use_defaults
172 	} config_mode;
173 
174 	enum ast_tx_chip tx_chip_type;
175 	u8 dp501_maxclk;
176 	u8 *dp501_fw_addr;
177 	const struct firmware *dp501_fw;	/* dp501 fw */
178 };
179 
to_ast_private(struct drm_device * dev)180 static inline struct ast_private *to_ast_private(struct drm_device *dev)
181 {
182 	return container_of(dev, struct ast_private, base);
183 }
184 
185 struct ast_private *ast_device_create(const struct drm_driver *drv,
186 				      struct pci_dev *pdev,
187 				      unsigned long flags);
188 
189 #define AST_IO_AR_PORT_WRITE		(0x40)
190 #define AST_IO_MISC_PORT_WRITE		(0x42)
191 #define AST_IO_VGA_ENABLE_PORT		(0x43)
192 #define AST_IO_SEQ_PORT			(0x44)
193 #define AST_IO_DAC_INDEX_READ		(0x47)
194 #define AST_IO_DAC_INDEX_WRITE		(0x48)
195 #define AST_IO_DAC_DATA		        (0x49)
196 #define AST_IO_GR_PORT			(0x4E)
197 #define AST_IO_CRTC_PORT		(0x54)
198 #define AST_IO_INPUT_STATUS1_READ	(0x5A)
199 #define AST_IO_MISC_PORT_READ		(0x4C)
200 
201 #define AST_IO_MM_OFFSET		(0x380)
202 
203 #define AST_IO_VGAIR1_VREFRESH		BIT(3)
204 
205 #define AST_IO_VGACRCB_HWC_ENABLED     BIT(1)
206 #define AST_IO_VGACRCB_HWC_16BPP       BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
207 
208 #define __ast_read(x) \
209 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
210 u##x val = 0;\
211 val = ioread##x(ast->regs + reg); \
212 return val;\
213 }
214 
215 __ast_read(8);
216 __ast_read(16);
217 __ast_read(32)
218 
219 #define __ast_io_read(x) \
220 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
221 u##x val = 0;\
222 val = ioread##x(ast->ioregs + reg); \
223 return val;\
224 }
225 
226 __ast_io_read(8);
227 __ast_io_read(16);
228 __ast_io_read(32);
229 
230 #define __ast_write(x) \
231 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
232 	iowrite##x(val, ast->regs + reg);\
233 	}
234 
235 __ast_write(8);
236 __ast_write(16);
237 __ast_write(32);
238 
239 #define __ast_io_write(x) \
240 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
241 	iowrite##x(val, ast->ioregs + reg);\
242 	}
243 
244 __ast_io_write(8);
245 __ast_io_write(16);
246 #undef __ast_io_write
247 
ast_set_index_reg(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t val)248 static inline void ast_set_index_reg(struct ast_private *ast,
249 				     uint32_t base, uint8_t index,
250 				     uint8_t val)
251 {
252 	ast_io_write16(ast, base, ((u16)val << 8) | index);
253 }
254 
255 void ast_set_index_reg_mask(struct ast_private *ast,
256 			    uint32_t base, uint8_t index,
257 			    uint8_t mask, uint8_t val);
258 uint8_t ast_get_index_reg(struct ast_private *ast,
259 			  uint32_t base, uint8_t index);
260 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
261 			       uint32_t base, uint8_t index, uint8_t mask);
262 
ast_open_key(struct ast_private * ast)263 static inline void ast_open_key(struct ast_private *ast)
264 {
265 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
266 }
267 
268 #define AST_VIDMEM_SIZE_8M    0x00800000
269 #define AST_VIDMEM_SIZE_16M   0x01000000
270 #define AST_VIDMEM_SIZE_32M   0x02000000
271 #define AST_VIDMEM_SIZE_64M   0x04000000
272 #define AST_VIDMEM_SIZE_128M  0x08000000
273 
274 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
275 
276 struct ast_vbios_stdtable {
277 	u8 misc;
278 	u8 seq[4];
279 	u8 crtc[25];
280 	u8 ar[20];
281 	u8 gr[9];
282 };
283 
284 struct ast_vbios_enhtable {
285 	u32 ht;
286 	u32 hde;
287 	u32 hfp;
288 	u32 hsync;
289 	u32 vt;
290 	u32 vde;
291 	u32 vfp;
292 	u32 vsync;
293 	u32 dclk_index;
294 	u32 flags;
295 	u32 refresh_rate;
296 	u32 refresh_rate_index;
297 	u32 mode_id;
298 };
299 
300 struct ast_vbios_dclk_info {
301 	u8 param1;
302 	u8 param2;
303 	u8 param3;
304 };
305 
306 struct ast_vbios_mode_info {
307 	const struct ast_vbios_stdtable *std_table;
308 	const struct ast_vbios_enhtable *enh_table;
309 };
310 
311 struct ast_crtc_state {
312 	struct drm_crtc_state base;
313 
314 	/* Last known format of primary plane */
315 	const struct drm_format_info *format;
316 
317 	struct ast_vbios_mode_info vbios_mode_info;
318 };
319 
320 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
321 
322 int ast_mode_config_init(struct ast_private *ast);
323 
324 #define AST_MM_ALIGN_SHIFT 4
325 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
326 
327 #define AST_DP501_FW_VERSION_MASK	GENMASK(7, 4)
328 #define AST_DP501_FW_VERSION_1		BIT(4)
329 #define AST_DP501_PNP_CONNECTED		BIT(1)
330 
331 #define AST_DP501_DEFAULT_DCLK	65
332 
333 #define AST_DP501_GBL_VERSION	0xf000
334 #define AST_DP501_PNPMONITOR	0xf010
335 #define AST_DP501_LINKRATE	0xf014
336 #define AST_DP501_EDID_DATA	0xf020
337 
338 /* Define for Soc scratched reg */
339 #define AST_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
340 //#define AST_VRAM_INIT_BY_BMC		BIT(7)
341 //#define AST_VRAM_INIT_READY		BIT(6)
342 
343 int ast_mm_init(struct ast_private *ast);
344 
345 /* ast post */
346 void ast_enable_vga(struct drm_device *dev);
347 void ast_enable_mmio(struct drm_device *dev);
348 bool ast_is_vga_enabled(struct drm_device *dev);
349 void ast_post_gpu(struct drm_device *dev);
350 u32 ast_mindwm(struct ast_private *ast, u32 r);
351 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
352 void ast_patch_ahb_2500(struct ast_private *ast);
353 /* ast dp501 */
354 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
355 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
356 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
357 u8 ast_get_dp501_max_clk(struct drm_device *dev);
358 void ast_init_3rdtx(struct drm_device *dev);
359 
360 #endif
361