1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7 #ifndef __AXG_H__ 8 #define __AXG_H__ 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 #define AXG_AOBUS_BASE 0xff800000 15 #define AXG_PERIPHS_BASE 0xff634400 16 #define AXG_HIU_BASE 0xff63c000 17 #define AXG_ETH_BASE 0xff3f0000 18 19 /* Always-On Peripherals registers */ 20 #define AXG_AO_ADDR(off) (AXG_AOBUS_BASE + ((off) << 2)) 21 22 #define AXG_AO_SEC_GP_CFG0 AXG_AO_ADDR(0x90) 23 #define AXG_AO_SEC_GP_CFG3 AXG_AO_ADDR(0x93) 24 #define AXG_AO_SEC_GP_CFG4 AXG_AO_ADDR(0x94) 25 #define AXG_AO_SEC_GP_CFG5 AXG_AO_ADDR(0x95) 26 27 #define AXG_AO_BOOT_DEVICE 0xF 28 #define AXG_AO_MEM_SIZE_MASK 0xFFFF0000 29 #define AXG_AO_MEM_SIZE_SHIFT 16 30 #define AXG_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000 31 #define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16 32 #define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF 33 34 /* Peripherals registers */ 35 #define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2)) 36 37 #define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50) 38 #define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51) 39 40 #define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0) 41 #define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2) 42 #define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) 43 #define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) 44 #define AXG_ETH_REG_0_PHY_CLK_EN BIT(10) 45 #define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11) 46 #define AXG_ETH_REG_0_CLK_EN BIT(12) 47 48 /* HIU registers */ 49 #define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2)) 50 51 #define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40) 52 53 /* Ethernet memory power domain */ 54 #define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) 55 56 #endif /* __AXG_H__ */ 57