1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  linux/include/asm-arm/arch-pxa/balloon3.h
4  *
5  *  Authors:	Nick Bane and Wookey
6  *  Created:	Oct, 2005
7  *  Copyright:	Toby Churchill Ltd
8  *  Cribbed from mainstone.c, by Nicholas Pitre
9  */
10 
11 #ifndef ASM_ARCH_BALLOON3_H
12 #define ASM_ARCH_BALLOON3_H
13 
14 #include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
15 
16 enum balloon3_features {
17 	BALLOON3_FEATURE_OHCI,
18 	BALLOON3_FEATURE_MMC,
19 	BALLOON3_FEATURE_CF,
20 	BALLOON3_FEATURE_AUDIO,
21 	BALLOON3_FEATURE_TOPPOLY,
22 };
23 
24 #define BALLOON3_FPGA_PHYS	PXA_CS4_PHYS
25 #define BALLOON3_FPGA_VIRT	IOMEM(0xf1000000)	/* as per balloon2 */
26 #define BALLOON3_FPGA_LENGTH	0x01000000
27 
28 #define	BALLOON3_FPGA_SETnCLR		(0x1000)
29 
30 /* FPGA / CPLD registers for CF socket */
31 #define	BALLOON3_CF_STATUS_REG		(BALLOON3_FPGA_VIRT + 0x00e00008)
32 #define	BALLOON3_CF_CONTROL_REG		(BALLOON3_FPGA_VIRT + 0x00e00008)
33 /* FPGA / CPLD version register */
34 #define	BALLOON3_FPGA_VER		(BALLOON3_FPGA_VIRT + 0x00e0001c)
35 /* FPGA / CPLD registers for NAND flash */
36 #define	BALLOON3_NAND_BASE		(PXA_CS4_PHYS + 0x00e00000)
37 #define	BALLOON3_NAND_IO_REG		(BALLOON3_FPGA_VIRT + 0x00e00000)
38 #define	BALLOON3_NAND_CONTROL2_REG	(BALLOON3_FPGA_VIRT + 0x00e00010)
39 #define	BALLOON3_NAND_STAT_REG		(BALLOON3_FPGA_VIRT + 0x00e00014)
40 #define	BALLOON3_NAND_CONTROL_REG	(BALLOON3_FPGA_VIRT + 0x00e00014)
41 
42 /* fpga/cpld interrupt control register */
43 #define BALLOON3_INT_CONTROL_REG	(BALLOON3_FPGA_VIRT + 0x00e0000C)
44 #define BALLOON3_VERSION_REG		(BALLOON3_FPGA_VIRT + 0x00e0001c)
45 
46 #define BALLOON3_SAMOSA_ADDR_REG	(BALLOON3_FPGA_VIRT + 0x00c00000)
47 #define BALLOON3_SAMOSA_DATA_REG	(BALLOON3_FPGA_VIRT + 0x00c00004)
48 #define BALLOON3_SAMOSA_STATUS_REG	(BALLOON3_FPGA_VIRT + 0x00c0001c)
49 
50 /* CF Status Register bits (read-only) bits */
51 #define BALLOON3_CF_nIRQ		(1 << 0)
52 #define BALLOON3_CF_nSTSCHG_BVD1	(1 << 1)
53 
54 /* CF Control Set Register bits / CF Control Clear Register bits (write-only) */
55 #define BALLOON3_CF_RESET		(1 << 0)
56 #define BALLOON3_CF_ENABLE		(1 << 1)
57 #define BALLOON3_CF_ADD_ENABLE		(1 << 2)
58 
59 /* CF Interrupt sources */
60 #define BALLOON3_BP_CF_NRDY_IRQ		BALLOON3_IRQ(0)
61 #define BALLOON3_BP_NSTSCHG_IRQ		BALLOON3_IRQ(1)
62 
63 /* NAND Control register */
64 #define	BALLOON3_NAND_CONTROL_FLWP	(1 << 7)
65 #define	BALLOON3_NAND_CONTROL_FLSE	(1 << 6)
66 #define	BALLOON3_NAND_CONTROL_FLCE3	(1 << 5)
67 #define	BALLOON3_NAND_CONTROL_FLCE2	(1 << 4)
68 #define	BALLOON3_NAND_CONTROL_FLCE1	(1 << 3)
69 #define	BALLOON3_NAND_CONTROL_FLCE0	(1 << 2)
70 #define	BALLOON3_NAND_CONTROL_FLALE	(1 << 1)
71 #define	BALLOON3_NAND_CONTROL_FLCLE	(1 << 0)
72 
73 /* NAND Status register */
74 #define	BALLOON3_NAND_STAT_RNB		(1 << 0)
75 
76 /* NAND Control2 register */
77 #define	BALLOON3_NAND_CONTROL2_16BIT	(1 << 0)
78 
79 /* GPIOs for irqs */
80 #define BALLOON3_GPIO_AUX_NIRQ		(94)
81 #define BALLOON3_GPIO_CODEC_IRQ		(95)
82 
83 /* Timer and Idle LED locations */
84 #define BALLOON3_GPIO_LED_NAND		(9)
85 #define BALLOON3_GPIO_LED_IDLE		(10)
86 
87 /* backlight control */
88 #define BALLOON3_GPIO_RUN_BACKLIGHT	(99)
89 
90 #define BALLOON3_GPIO_S0_CD		(105)
91 
92 /* NAND */
93 #define BALLOON3_GPIO_RUN_NAND		(102)
94 
95 /* PCF8574A Leds */
96 #define	BALLOON3_PCF_GPIO_BASE		160
97 #define	BALLOON3_PCF_GPIO_LED0		(BALLOON3_PCF_GPIO_BASE + 0)
98 #define	BALLOON3_PCF_GPIO_LED1		(BALLOON3_PCF_GPIO_BASE + 1)
99 #define	BALLOON3_PCF_GPIO_LED2		(BALLOON3_PCF_GPIO_BASE + 2)
100 #define	BALLOON3_PCF_GPIO_LED3		(BALLOON3_PCF_GPIO_BASE + 3)
101 #define	BALLOON3_PCF_GPIO_LED4		(BALLOON3_PCF_GPIO_BASE + 4)
102 #define	BALLOON3_PCF_GPIO_LED5		(BALLOON3_PCF_GPIO_BASE + 5)
103 #define	BALLOON3_PCF_GPIO_LED6		(BALLOON3_PCF_GPIO_BASE + 6)
104 #define	BALLOON3_PCF_GPIO_LED7		(BALLOON3_PCF_GPIO_BASE + 7)
105 
106 /* FPGA Interrupt Mask/Acknowledge Register */
107 #define BALLOON3_INT_S0_IRQ		(1 << 0)  /* PCMCIA 0 IRQ */
108 #define BALLOON3_INT_S0_STSCHG		(1 << 1)  /* PCMCIA 0 status changed */
109 
110 /* CPLD (and FPGA) interface definitions */
111 #define CPLD_LCD0_DATA_SET             0x00
112 #define CPLD_LCD0_DATA_CLR             0x10
113 #define CPLD_LCD0_COMMAND_SET          0x01
114 #define CPLD_LCD0_COMMAND_CLR          0x11
115 #define CPLD_LCD1_DATA_SET             0x02
116 #define CPLD_LCD1_DATA_CLR             0x12
117 #define CPLD_LCD1_COMMAND_SET          0x03
118 #define CPLD_LCD1_COMMAND_CLR          0x13
119 
120 #define CPLD_MISC_SET                  0x07
121 #define CPLD_MISC_CLR                  0x17
122 #define CPLD_MISC_LOON_NRESET_BIT      0
123 #define CPLD_MISC_LOON_UNSUSP_BIT      1
124 #define CPLD_MISC_RUN_5V_BIT           2
125 #define CPLD_MISC_CHG_D0_BIT           3
126 #define CPLD_MISC_CHG_D1_BIT           4
127 #define CPLD_MISC_DAC_NCS_BIT          5
128 
129 #define CPLD_LCD_SET                   0x08
130 #define CPLD_LCD_CLR                   0x18
131 #define CPLD_LCD_BACKLIGHT_EN_0_BIT    0
132 #define CPLD_LCD_BACKLIGHT_EN_1_BIT    1
133 #define CPLD_LCD_LED_RED_BIT           4
134 #define CPLD_LCD_LED_GREEN_BIT         5
135 #define CPLD_LCD_NRESET_BIT            7
136 
137 #define CPLD_LCD_RO_SET                0x09
138 #define CPLD_LCD_RO_CLR                0x19
139 #define CPLD_LCD_RO_LCD0_nWAIT_BIT     0
140 #define CPLD_LCD_RO_LCD1_nWAIT_BIT     1
141 
142 #define CPLD_SERIAL_SET                0x0a
143 #define CPLD_SERIAL_CLR                0x1a
144 #define CPLD_SERIAL_GSM_RI_BIT         0
145 #define CPLD_SERIAL_GSM_CTS_BIT        1
146 #define CPLD_SERIAL_GSM_DTR_BIT        2
147 #define CPLD_SERIAL_LPR_CTS_BIT        3
148 #define CPLD_SERIAL_TC232_CTS_BIT      4
149 #define CPLD_SERIAL_TC232_DSR_BIT      5
150 
151 #define CPLD_SROUTING_SET              0x0b
152 #define CPLD_SROUTING_CLR              0x1b
153 #define CPLD_SROUTING_MSP430_LPR       0
154 #define CPLD_SROUTING_MSP430_TC232     1
155 #define CPLD_SROUTING_MSP430_GSM       2
156 #define CPLD_SROUTING_LOON_LPR         (0 << 4)
157 #define CPLD_SROUTING_LOON_TC232       (1 << 4)
158 #define CPLD_SROUTING_LOON_GSM         (2 << 4)
159 
160 #define CPLD_AROUTING_SET              0x0c
161 #define CPLD_AROUTING_CLR              0x1c
162 #define CPLD_AROUTING_MIC2PHONE_BIT    0
163 #define CPLD_AROUTING_PHONE2INT_BIT    1
164 #define CPLD_AROUTING_PHONE2EXT_BIT    2
165 #define CPLD_AROUTING_LOONL2INT_BIT    3
166 #define CPLD_AROUTING_LOONL2EXT_BIT    4
167 #define CPLD_AROUTING_LOONR2PHONE_BIT  5
168 #define CPLD_AROUTING_LOONR2INT_BIT    6
169 #define CPLD_AROUTING_LOONR2EXT_BIT    7
170 
171 /* Balloon3 Interrupts */
172 #define BALLOON3_IRQ(x)		(IRQ_BOARD_START + (x))
173 
174 #define BALLOON3_AUX_NIRQ	PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
175 #define BALLOON3_CODEC_IRQ	PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
176 
177 #define BALLOON3_NR_IRQS	(IRQ_BOARD_START + 16)
178 
179 extern int balloon3_has(enum balloon3_features feature);
180 
181 #endif
182