1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_PRIVATE_H 8 #define PLAT_PRIVATE_H 9 10 #ifndef __ASSEMBLER__ 11 12 #include <stdint.h> 13 14 #include <lib/psci/psci.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 #include <lib/mmio.h> 17 #include <plat_params.h> 18 19 #define __sramdata __attribute__((section(".sram.data"))) 20 #define __sramconst __attribute__((section(".sram.rodata"))) 21 #define __sramfunc __attribute__((section(".sram.text"))) 22 23 #define __pmusramdata __attribute__((section(".pmusram.data"))) 24 #define __pmusramconst __attribute__((section(".pmusram.rodata"))) 25 #define __pmusramfunc __attribute__((section(".pmusram.text"))) 26 27 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 28 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 29 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; 30 extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end; 31 extern uint32_t __sram_incbin_start, __sram_incbin_end; 32 extern uint32_t __sram_incbin_real_end; 33 34 /****************************************************************************** 35 * The register have write-mask bits, it is mean, if you want to set the bits, 36 * you needs set the write-mask bits at the same time, 37 * The write-mask bits is in high 16-bits. 38 * The fllowing macro definition helps access write-mask bits reg efficient! 39 ******************************************************************************/ 40 #define REG_MSK_SHIFT 16 41 42 #ifndef WMSK_BIT 43 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 44 #endif 45 46 /* set one bit with write mask */ 47 #ifndef BIT_WITH_WMSK 48 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 49 #endif 50 51 #ifndef BITS_SHIFT 52 #define BITS_SHIFT(bits, shift) (bits << (shift)) 53 #endif 54 55 #ifndef BITS_WITH_WMASK 56 #define BITS_WITH_WMASK(bits, msk, shift)\ 57 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 58 #endif 59 60 /****************************************************************************** 61 * Function and variable prototypes 62 *****************************************************************************/ 63 #ifdef __aarch64__ 64 void plat_configure_mmu_el3(unsigned long total_base, 65 unsigned long total_size, 66 unsigned long, 67 unsigned long, 68 unsigned long, 69 unsigned long); 70 71 void rockchip_plat_mmu_el3(void); 72 #else 73 void plat_configure_mmu_svc_mon(unsigned long total_base, 74 unsigned long total_size, 75 unsigned long, 76 unsigned long, 77 unsigned long, 78 unsigned long); 79 80 void rockchip_plat_mmu_svc_mon(void); 81 #endif 82 83 void plat_cci_init(void); 84 void plat_cci_enable(void); 85 void plat_cci_disable(void); 86 87 void plat_delay_timer_init(void); 88 89 void params_early_setup(u_register_t plat_params_from_bl2); 90 91 void plat_rockchip_gic_driver_init(void); 92 void plat_rockchip_gic_init(void); 93 void plat_rockchip_gic_cpuif_enable(void); 94 void plat_rockchip_gic_cpuif_disable(void); 95 void plat_rockchip_gic_pcpu_init(void); 96 97 void plat_rockchip_pmu_init(void); 98 void plat_rockchip_soc_init(void); 99 uintptr_t plat_get_sec_entrypoint(void); 100 101 void platform_cpu_warmboot(void); 102 103 struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void); 104 struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void); 105 struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 106 struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void); 107 void plat_rockchip_gpio_init(void); 108 void plat_rockchip_save_gpio(void); 109 void plat_rockchip_restore_gpio(void); 110 111 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); 112 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 113 plat_local_state_t lvl_state); 114 int rockchip_soc_cores_pwr_dm_off(void); 115 int rockchip_soc_sys_pwr_dm_suspend(void); 116 int rockchip_soc_cores_pwr_dm_suspend(void); 117 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 118 plat_local_state_t lvl_state); 119 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 120 plat_local_state_t lvl_state); 121 int rockchip_soc_cores_pwr_dm_on_finish(void); 122 int rockchip_soc_sys_pwr_dm_resume(void); 123 124 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 125 plat_local_state_t lvl_state); 126 int rockchip_soc_cores_pwr_dm_resume(void); 127 void __dead2 rockchip_soc_soft_reset(void); 128 void __dead2 rockchip_soc_system_off(void); 129 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( 130 const psci_power_state_t *target_state); 131 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); 132 133 extern const unsigned char rockchip_power_domain_tree_desc[]; 134 135 extern void *pmu_cpuson_entrypoint; 136 extern u_register_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 137 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 138 139 extern const mmap_region_t plat_rk_mmap[]; 140 141 uint32_t rockchip_get_uart_base(void); 142 uint32_t rockchip_get_uart_baudrate(void); 143 uint32_t rockchip_get_uart_clock(void); 144 145 #endif /* __ASSEMBLER__ */ 146 147 /****************************************************************************** 148 * cpu up status 149 * The bits of macro value is not more than 12 bits for cmp instruction! 150 ******************************************************************************/ 151 #define PMU_CPU_HOTPLUG 0xf00 152 #define PMU_CPU_AUTO_PWRDN 0xf0 153 #define PMU_CLST_RET 0xa5 154 155 #endif /* PLAT_PRIVATE_H */ 156