1 /* 2 * Copyright (c) 2016 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BRCM_DEF_H 8 #define BRCM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <lib/utils_def.h> 13 #include <lib/xlat_tables/xlat_tables.h> 14 #include <plat/common/common_def.h> 15 16 #include <platform_def.h> 17 18 #define PLAT_PHY_ADDR_SPACE_SIZE BIT_64(32) 19 #define PLAT_VIRT_ADDR_SPACE_SIZE BIT_64(32) 20 21 #define BL11_DAUTH_ID 0x796C51ab 22 #define BL11_DAUTH_BASE BL11_RW_BASE 23 24 /* We keep a table at the end of ROM for function pointers */ 25 #define ROM_TABLE_SIZE 32 26 #define BL1_ROM_TABLE (BL1_RO_LIMIT - ROM_TABLE_SIZE) 27 28 /* 29 * The top 16MB of DRAM1 is configured as secure access only using the TZC 30 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 31 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 32 */ 33 #define BRCM_TZC_DRAM1_SIZE ULL(0x01000000) 34 35 #define BRCM_SCP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \ 36 BRCM_DRAM1_SIZE - \ 37 BRCM_SCP_TZC_DRAM1_SIZE) 38 #define BRCM_SCP_TZC_DRAM1_SIZE PLAT_BRCM_SCP_TZC_DRAM1_SIZE 39 40 #define BRCM_AP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \ 41 BRCM_DRAM1_SIZE - \ 42 BRCM_TZC_DRAM1_SIZE) 43 #define BRCM_AP_TZC_DRAM1_SIZE (BRCM_TZC_DRAM1_SIZE - \ 44 BRCM_SCP_TZC_DRAM1_SIZE) 45 46 #define BRCM_NS_DRAM1_BASE BRCM_DRAM1_BASE 47 #define BRCM_NS_DRAM1_SIZE (BRCM_DRAM1_SIZE - \ 48 BRCM_TZC_DRAM1_SIZE) 49 50 #ifdef BRCM_SHARED_DRAM_BASE 51 #define BRCM_NS_SHARED_DRAM_BASE BRCM_SHARED_DRAM_BASE 52 #define BRCM_NS_SHARED_DRAM_SIZE BRCM_SHARED_DRAM_SIZE 53 #endif 54 55 #define BRCM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 56 BRCM_SHARED_RAM_BASE, \ 57 BRCM_SHARED_RAM_SIZE, \ 58 MT_DEVICE | MT_RW | MT_SECURE) 59 60 #define BRCM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 61 BRCM_NS_DRAM1_BASE, \ 62 BRCM_NS_DRAM1_SIZE, \ 63 MT_MEMORY | MT_RW | MT_NS) 64 65 #ifdef BRCM_SHARED_DRAM_BASE 66 #define BRCM_MAP_NS_SHARED_DRAM MAP_REGION_FLAT( \ 67 BRCM_NS_SHARED_DRAM_BASE, \ 68 BRCM_NS_SHARED_DRAM_SIZE, \ 69 MT_MEMORY | MT_RW | MT_NS) 70 #endif 71 72 #ifdef BRCM_EXT_SRAM_BASE 73 #define BRCM_MAP_EXT_SRAM MAP_REGION_FLAT( \ 74 BRCM_EXT_SRAM_BASE, \ 75 BRCM_EXT_SRAM_SIZE, \ 76 MT_DEVICE | MT_RW | MT_SECURE) 77 #endif 78 79 #define BRCM_MAP_NAND_RO MAP_REGION_FLAT(NAND_BASE_ADDR,\ 80 NAND_SIZE, \ 81 MT_MEMORY | MT_RO | MT_SECURE) 82 83 #define BRCM_MAP_QSPI_RO MAP_REGION_FLAT(QSPI_BASE_ADDR,\ 84 QSPI_SIZE, \ 85 MT_MEMORY | MT_RO | MT_SECURE) 86 87 #define HSLS_REGION MAP_REGION_FLAT(HSLS_BASE_ADDR, \ 88 HSLS_SIZE, \ 89 MT_DEVICE | MT_RW | MT_SECURE) 90 91 #define CCN_REGION MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \ 92 CCN_SIZE, \ 93 MT_DEVICE | MT_RW | MT_SECURE) 94 95 #define GIC500_REGION MAP_REGION_FLAT(GIC500_BASE, \ 96 GIC500_SIZE, \ 97 MT_DEVICE | MT_RW | MT_SECURE) 98 #ifdef PERIPH0_BASE 99 #define PERIPH0_REGION MAP_REGION_FLAT(PERIPH0_BASE, \ 100 PERIPH0_SIZE, \ 101 MT_DEVICE | MT_RW | MT_SECURE) 102 #endif 103 104 #ifdef PERIPH1_BASE 105 #define PERIPH1_REGION MAP_REGION_FLAT(PERIPH1_BASE, \ 106 PERIPH1_SIZE, \ 107 MT_DEVICE | MT_RW | MT_SECURE) 108 #endif 109 110 #ifdef PERIPH2_BASE 111 #define PERIPH2_REGION MAP_REGION_FLAT(PERIPH2_BASE, \ 112 PERIPH2_SIZE, \ 113 MT_DEVICE | MT_RW | MT_SECURE) 114 #endif 115 116 #if BRCM_BL31_IN_DRAM 117 #if IMAGE_BL2 118 #define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 119 BL31_BASE, \ 120 PLAT_BRCM_MAX_BL31_SIZE,\ 121 MT_DEVICE | MT_RW | MT_SECURE) 122 #else 123 #define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 124 BL31_BASE, \ 125 PLAT_BRCM_MAX_BL31_SIZE,\ 126 MT_MEMORY | MT_RW | MT_SECURE) 127 #endif 128 #endif 129 130 #if defined(USB_BASE) && defined(DRIVER_USB_ENABLE) 131 #define USB_REGION MAP_REGION_FLAT( \ 132 USB_BASE, \ 133 USB_SIZE, \ 134 MT_DEVICE | MT_RW | MT_SECURE) 135 #endif 136 137 #ifdef USE_CRMU_SRAM 138 #define CRMU_SRAM_REGION MAP_REGION_FLAT( \ 139 CRMU_SRAM_BASE, \ 140 CRMU_SRAM_SIZE, \ 141 MT_DEVICE | MT_RW | MT_SECURE) 142 #endif 143 /* 144 * The number of regions like RO(code), coherent and data required by 145 * different BL stages which need to be mapped in the MMU. 146 */ 147 #if USE_COHERENT_MEM 148 #define BRCM_BL_REGIONS 3 149 #else 150 #define BRCM_BL_REGIONS 2 151 #endif 152 153 #endif /* BRCM_DEF_H */ 154